Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 143 / 1898

1:132 Volume 1, Part 1: IA-32 Application Execution Model in an Intel
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Itanium
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System Environment
(last byte of a multiple byte operand or instruction) is truncated (wrapped) at the
4G-byte virtual boundary
• IA-32 64-bit Address Generation: The resultant 32-bit virtual address is
converted into a 64-bit virtual address by zero extending to 64-bits, this places all
IA-32 instruction set memory references within the first 4G-bytes of the 64-bit
virtual address space within virtual region 0.
If IA-32 code is utilizing a flat segmented model (segment bases are set to zero) then
IA-32 and Itanium architecture-based code can freely exchange pointers after a pointer
has been zero extended to 64-bits. For segmented IA-32 code, effective address
pointers must be first transformed into a virtual address before they are shared with
Itanium architecture-based code.
6.2.3.3 Self Modifying Code
While operating in the IA-32 instruction set, self modifying code and instruction cache
coherency (coherency with respect to the local processor’s data cache) is supported for
all IA-32 programs. Self modifying code detection is directly supported at the same
level of compatibility as the Pentium processor
. Software must insert an IA-32 branch
instruction between the store operation and the instruction modified for the updated
instruction bytes to be recognized.
It is undefined whether the processor will detect a IA-32 self modifying code event for
the following conditions; 1) PSR.dt or PSR.it is 0, or 2) there are virtual aliases to
different physical addresses between the instruction and data TLBs. To ensure self
modifying code works correctly for IA-32 applications, the operating system must
ensure that there are no virtual aliases to different physical addresses between the
instruction and data TLBs.
When switching from the Itanium instruction set to the IA-32 instruction set, and while
executing Itanium instructions, self modifying code and instruction cache coherency are
not directly supported by the processor hardware. Specifically, if a modification is made
to IA-32 instructions by Itanium instructions, Itanium architecture-based code must
explicitly synchronize the instruction caches with the code sequence defined in
“Memory Consistency” on page 1:72 . Otherwise the modification may or may not be
observed by subsequent IA-32 instructions.
When switching from the IA-32 to the Itanium instruction sets, modification of the local
instruction cache contents by IA-32 instructions is detected by the processor hardware.
The processor ensures that the instruction cache is made coherent with respect to the
modification and all subsequent Itanium instruction fetches see the modification.
6.2.3.4 Memory Ordering Interactions
IA-32 instructions are mapped into the Itanium memory ordering model as follows:
• All IA-32 stores have release semantics
• All IA-32 loads have acquire semantics
• All IA-32 read-modify-write or lock instructions have release and acquire
semantics (fully fenced).