Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 1125 / 1898

3:226 Volume 3: Instruction Reference
pshradd
pshradd — Parallel Shift Right and Add
Format: (
qp
) pshradd2
r
1
=
r
2
, count
2
,
r
3
A10
Description:
The four signed 16-bit data elements of GR
r
2
are each independently shifted to the
right by count
2
bits, and added to the four signed 16-bit data elements of GR
r
3
. The
right shift operation fills the high-order bits of each element with the initial value of the
sign bits of the data elements in GR
r
2
. The add operation is performed with signed
saturation. The four signed 16-bit results of the add are placed in GR
r
1
. The first
operand can be shifted by 1, 2 or 3 bits.
Operation: if (PR[ qp ]) {
check_target_register( r
1
);
x[0] = GR[ r
2
]{15:0}; y[0] = GR[ r
3
]{15:0};
x[1] = GR[ r
2
]{31:16}; y[1] = GR[ r
3
]{31:16};
x[2] = GR[ r
2
]{47:32}; y[2] = GR[ r
3
]{47:32};
x[3] = GR[ r
2
]{63:48}; y[3] = GR[ r
3
]{63:48};
max = sign_ext(0x7fff, 16);
min = sign_ext(0x8000, 16);
for (i = 0; i < 4; i++) {
temp[i] = shift_right_signed(sign_ext(x[i], 16), count
2
);
res[i] = temp[i] + sign_ext(y[i], 16);
if (res[i] > max)
res[i] = max;
if (res[i] < min)
res[i] = min;
}
GR[ r
1
] = concatenate4(res[3], res[2], res[1], res[0]);
GR[ r
1
].nat = GR[ r
2
].nat || GR[ r
3
].nat;
}
Interruptions:
Illegal Operation fault