Volume 3: Instruction Reference
3:151
ld
ld — Load
Format:
(
qp
) ld
sz
.
ldtype
.
ldhint r
1
= [
r
3
]
no_base_update_form
(
qp
) ld
sz
.
ldtype
.
ldhint r
1
= [
r
3
],
r
2
reg_base_update_form
(
qp
) ld
sz
.
ldtype
.
ldhint r
1
= [
r
3
],
imm
9
imm_base_update_form
(
qp
) ld16.
ldhint r
1
, ar.csd = [
r
3
]
sixteen_byte_form, no_base_update_form
(
qp
) ld16.acq.
ldhint r
1
, ar.csd = [
r
3
]
sixteen_byte_form, acquire_form,
no_base_update_form
(
qp
) ld8.fill.
ldhint r
1
= [
r
3
]
fill_form, no_base_update_form
(
qp
) ld8.fill.
ldhint r
1
= [
r
3
],
r
2
fill_form, reg_base_update_form
(
qp
) ld8.fill.
ldhint r
1
= [
r
3
],
imm
9
fill_form, imm_base_update_form
Description:
A value consisting of
sz
bytes is read from memory starting at the address specified by
the value in GR
r
3
. The value is then zero extended and placed in GR
r
1
. The values of
the
sz
completer are given in
. The NaT bit corresponding to GR
r
1
is cleared,
except as described below for speculative loads. The
ldtype
completer specifies special
load operations, which are described in
For the sixteen_byte_form, two 8-byte values are loaded as a single, 16-byte memory
read. The value at the lowest address is placed in GR
r
1
, and the value at the highest
address is placed in the Compare and Store Data application register (AR[CSD]). The
only load types supported for this sixteen_byte_form are
none
and
acq
.
For the fill_form, an 8-byte value is loaded, and a bit in the UNAT application register is
copied into the target register NaT bit. This instruction is used for reloading a spilled
register/NaT pair. See
Section 4.4.4, “Control Speculation” on page 1:60
for details.
In the base update forms, the value in GR
r
3
is added to either a signed immediate
value (
imm
9
) or a value from GR
r
2
, and the result is placed back in GR
r
3
. This base
register update is done after the load, and does not affect the load address. In the
reg_base_update_form, if the NaT bit corresponding to GR
r
2
is set, then the NaT bit
corresponding to GR
r
3
is set and no fault is raised. Base register update is not
supported for the
ld16
instruction.
Table 2-32.
sz
Completers
sz
Completer
Bytes Accessed
1
1 byte
2
2 bytes
4
4 bytes
8
8 bytes
Table 2-33.
Load Types
ldtype
Completer
Interpretation
Special Load Operation
none
Normal load
s
Speculative load
Certain exceptions may be deferred rather than generating a fault.
Deferral causes the target register’s NaT bit to be set. The NaT bit is
later used to detect deferral.
a
Advanced load
An entry is added to the ALAT. This allows later instructions to check for
colliding stores. If the referenced data page has a non-speculative
attribute, the target register and NaT bit is cleared, and the processor
ensures that no ALAT entry exists for the target register. The absence of
an ALAT entry is later used to detect deferral or collision.
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...