Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 71 / 1898

1:60 Volume 1, Part 1: Application Programming Model
Three types of atomic semaphore operations are defined: exchange (
xchg
); compare
and exchange (
cmpxchg
); and fetch and add (
fetchadd
).
The
xchg
target is loaded with the zero-extended contents of the memory location
addressed by the first source and then the second source is stored into the same
memory location.
The
cmpxchg
target is loaded with the zero-extended contents of the memory location
addressed by the first source; if the zero-extended value is equal to the contents of the
Compare and Exchange Compare Value application register (CCV), then the second
source is stored into the same memory location. The
cmp8xchg16
instruction loads the
target with 8 bytes from the memory location addressed by the first source; if this
value is equal to the contents of the CCV register, then the second source and the CSD
register are both stored into memory at the 16-byte-aligned address which contains the
memory location loaded.
The
fetchadd
instruction specifies one general register source, one general register
target, and an immediate. The
fetchadd
target is loaded with the zero-extended
contents of the memory location addressed by the source and then the immediate is
added to the loaded value and the result is stored into the same memory location.
4.4.4 Control Speculation
Special mechanisms are provided to allow for compiler-directed speculation. This
speculation takes two forms, control speculation and data speculation, with a separate
mechanism to support each. See also
“Data Speculation” on page 1:63 .
4.4.4.1 Control Speculation Concepts
Control speculation describes the compiler optimization where an instruction or a
sequence of instructions is executed before it is known that the dynamic control flow of
the program will actually reach the point in the program where the sequence of
instructions is needed. This is done with instruction sequences that have long execution
latencies. Starting the execution early allows the compiler to overlap the execution with
other work, increasing the parallelism and decreasing overall execution time. The
compiler performs this optimization when it determines that it is very likely that the
dynamic control flow of the program will eventually require this calculation. In cases
where the control flow is such that the calculation turns out not to be needed, its results
are simply discarded (the results in processor registers are simply not used).
Since the speculative instruction sequence may not be required by the program, no
exceptions encountered that would be visible to the program can be signalled until it is
determined that the program’s control flow does require the execution of this
instruction sequence. For this reason, a mechanism is provided for recording the
occurrence of an exception so that it can be signalled later if and when it is necessary.
In such a situation, the exception is said to be deferred. When an exception is deferred
by an instruction, a special token is written into the target register to indicate the
existence of a deferred exception in the program.
Deferred exception tokens are represented differently in the general and floating-point
register files. In general registers, an additional bit is defined for each register called
the NaT bit (Not a Thing). Thus general registers are 65 bits wide. A NaT bit equal to 1