Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 128 / 1898

Volume 1, Part 1: IA-32 Application Execution Model in an Intel
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Itanium
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System Environment 1:117
6.2.2.1 IA-32 General Purpose Registers
Integer registers are mapped into the lower 32-bits of Itanium general registers GR8 to
GR15. Values in the upper 32-bits of GR8 to GR15 are ignored on entry to IA-32
execution. After the IA-32 instruction set completes execution, the upper 32-bits of
GR8 - GR15 are sign-extended from bit 31.
Based on IA-32 and Itanium calling conventions, the required IA-32 state must be
loaded in memory or registers by Itanium architecture-based code before entering the
IA-32 instruction set.
6.2.2.2 IA-32 Instruction Pointer
The processor maintains two instruction pointers for IA-32 instruction set references,
EIP (32-bit effective address) and IP (a 64-bit virtual address equivalent to the Itanium
instruction set IP). IP is generated by adding the code segment base to EIP and zero
extending to 64-bits. IP should not be confused with the 16-bit effective address
instruction pointer of the 8086. EIP is an offset within the current code segment, while
IP is a 64-bit virtual pointer shared with the Itanium instruction set. The following
relationship is defined between EIP and IP while executing IA-32 instructions.
IP{63:32} = 0;
IP{31:0} = EIP{31:0} + CSD.Base;
PFS
unmodified
not used for IA-32 code execution, Prior
EC is preserved in PFM
Intel
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Itanium
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preserved registers
LC
EC
EFLAG
EFLAG
IA-32 state
32 IA-32 System/Arithmetic flags,
writes of some bits condition by CPL and
EFLAG.iopl.
CSD CSD 64 IA-32 code segment (register format)
b
SSD SSD IA-32 stack segment (register format)
b
CFLG CR0/CR4 64 IA-32 control flags
CR0=CFLG{31:0}, CR4=CFLG{63:32},
writable at CPL=0 only.
a. On transitions into the IA-32 instruction set the upper 32-bits are ignored. On exit the upper 32-bits are sign
extended from bit 31.
b. Segment descriptor formats differ from the iA-32 memory format, see “IA-32 Segment Registers” on
page 1:118 for details. Modification of a selector or descriptor does not set the access/busy bit in memory.
c. The GDT/LDT descriptors are NOT protected from modification by Itanium architecture-based user level code
d. All registers in the current and prior registers frames are left in an undefined state after IA-32 execution.
Software must preserve these values before entering the IA-32 instruction set.
e. IA-32 floating-point register mappings are physical and do not reflect the IA-32 top of stack value.
f. These registers are used by the processor and may be left an undefined state following IA-32 instruction set
execution. Software should preserve required values before entering IA-32 code.
Figure 6-3. IA-32 General Registers (GR8 to GR15)
63 32 31 0
sign extended EAX.. EDI{31:0}
Table 6-1. IA-32 Application Register Mapping (Continued)
Intel
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Itanium
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Reg IA-32 Reg Convention Size Description