Volume 2, Part 1: Itanium
®
Architecture-based Operating System Interaction Model with IA-32 Applications
2:273
IN
[mf]
//Fence prior memory references, if required
add port_addr = IO_Port_Base, Expanded_Port_Number
ld.acq data, (port_addr)
[mf.a] //Wait for platform acceptance, if required
[mf]
//Fence future memory references, if required
10.8
Debug Model
The debug facilitates defined by the Itanium architecture are designed to support
debugging of both the Itanium and IA-32 instruction set. The following debug events
can be triggered during IA-32 instruction set execution by Itanium debug resources.
•
Single Step trap
–
When PSR.ss is 1 (or EFLAG.tf is 1), successful execution of
each IA-32 instruction, results in an IA_32_Exception(Debug) trap. After the single
step trap, IIP points to the next IA-32 instruction to be executed.
•
Breakpoint Instruction trap
–
execution of INT 3 (breakpoint) instruction results
in a IA_32_Exception(Debug) trap.
•
Instruction Debug fault
–
When PSR.db is 1 and PSR.id is 0 and EFLAG.rf is 0,
any IA-32 instruction fetch that matches the parameters specified by the IBR
registers results in an IA_32_Exception(Debug) fault. After servicing a Debug fault,
debuggers can set PSR.id (or EFLAG.rf for IA-32 instructions) before restarting the
faulting instruction. If PSR.id is 1, Instruction Debug faults are temporarily disabled
for one Itanium instruction. If PSR.id is 1 or EFLAG.rf is 1, Instruction Debug faults
are temporarily disabled for one IA-32 instruction. The successful execution of an
IA-32 instruction clears both PSR.id and EFLAG.rf bits. The successful execution of
an Itanium instruction only clears PSR.id.
•
Data Debug traps
–
When PSR.db is 1, any IA-32 data memory reference that
matches the parameters specified by the DBR registers results in a
IA_32_Exception(Debug) trap. IA-32 data debug events are traps, not faults as
defined for Itanium instruction set data debug events. Trap behavior is required
since any given IA-32 instruction can access several memory locations during its
execution. The reported trap code returns the match status of the first four DBR
registers that matched during the execution of the IA-32 instruction. Zero, one or
DBR registers may be reported as matching.
•
Taken Branch trap
–
When PSR.tb is 1, a IA_32_Exception(Debug) trap occurs on
every IA-32 taken branch instruction (CALL, Jcc, JMP, RET, LOOP). After the trap,
IIP points to the branch target.
•
Lower Privilege Transfer trap
–
Does not occur during IA-32 instruction set
execution.
For virtual memory accesses, breakpoint address registers contain the virtual addresses
of the debug breakpoint. For physical accesses, the addresses in these registers are
treated as a physical address. Software should be aware that debug registers
configured to fault on virtual references, may also fault on a physical reference if
translations are disabled. Likewise a debug register configured for physical references
can fault on virtual references that match the debug breakpoint registers.
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...