Volume 3: Instruction Reference
3:233
ptc.l
ptc.l — Purge Local Translation Cache
Format:
(
qp
) ptc.l
r
3
,
r
2
Description:
The instruction and data translation cache of the local processor is searched for all
entries whose virtual address and page size partially or completely overlap the specified
purge virtual address and purge address range. All these entries are removed.
The purge virtual address is specified by GR
r
3
bits{60:0} and the purge region
identifier is selected by GR
r
3
bits {63:61}. GR
r
2
specifies the address range of the
purge as 1<<GR[
r
2
]{7:2} bytes in size. See
Section 4.1.1.7, “Page Sizes” on page 2:57
for details on supported page sizes for TLB purges.
The processor ensures that all entries matching the purging parameters are removed.
However, based on the processor model, the translation cache may be also purged of
more translations than specified by the purge parameters up to and including removal
of all entries within the translation cache.
This instruction can only be executed at the most privileged level, and when PSR.vm is
0.
This is a local operation, no purge broadcast to other processors occurs in a
multiprocessor system. This instruction ensures that all prior stores are made locally
visible before the actual purge operation is performed.
Operation:
if (PR[
qp
]) {
if (PSR.cpl != 0)
privileged_operation_fault(0);
if (GR[
r
3
].nat || GR[
r
2
].nat)
register_nat_consumption_fault(0);
if (unimplemented_virtual_address(GR[
r
3
], PSR.vm))
unimplemented_data_address_fault(0);
if (PSR.vm == 1)
virtualization_fault();
tmp_rid = RR[GR[
r
3
]{63:61}].rid;
tmp_va = GR[
r
3
]{60:0};
tmp_size = GR[
r
2
]{7:2};
tmp_va = align_to_size_boundary(tmp_va, tmp_size);
tlb_must_purge_dtc_entries(tmp_rid, tmp_va, tmp_size);
tlb_must_purge_itc_entries(tmp_rid, tmp_va, tmp_size);
}
Interruptions:
Machine Check abort
Unimplemented Data Address fault
Privileged Operation fault
Virtualization fault
Register NaT Consumption fault
Serialization:
Software must issue the appropriate data and/or instruction serialization operation to
ensure the purge is completed before a data access, non-access reference, or
instruction fetch access dependent upon the purge.
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...