Volume 2, Part 1: Addressing and Protection
2:57
Software can verify page level permissions by the
probe
(regular_form
probe
or
probe.fault
) instruction, which checks accessibility to a given virtual page by verifying
privilege levels, page level read and write permission, and protection key read and
write permission.
Execute-only pages (TLB.ar 7) can be used to promote the privilege level on entry into
the operating system. User level code would typically branch into a promotion page
(controlled by the operating system) and execute the Enter Privileged Code (
epc
)
instruction. When
epc
successfully promotes, the next instruction group is executed at
the target privilege level specified by the promotion page. A procedure return branch
type (
br.ret
) can demote the current privilege level.
4.1.1.7
Page Sizes
A range of page sizes are supported to assist software in mapping system resources
and improve TLB/VHPT utilization. Typically, operating systems will select a small range
of fixed page sizes to implement virtual memory algorithms. Larger pages may be
statically allocated. For example, large areas of the virtual address space may be
reserved for operating system kernels, frame buffers, or memory-mapped I/O regions.
Software may also elect to pin these translations, by placing them in the translation
registers.
lists insertable and purgeable page sizes that are supported by all processor
models. Insertable page sizes can be specified in the translation cache, the translation
registers, the region registers and the VHPT. Insertable page sizes can also be used as
parameters to TLB purge instructions (
ptc.l
,
ptc.g
,
ptc.ga
or
ptr
). Page sizes that
are purgeable only may only be used as parameters to TLB purge instructions.
Processors may also support additional insertable and purgeable page sizes. Please see
the processor-specific documentation for further information on the page sizes
supported by the Itanium processor.
6
3
RWX
RW
RW
RW
read, write, execute / read, write
2
–
RWX
RW
RW
1
–
–
RWX
RW
0
–
–
–
RW
7
3
X
X
X
RX
exec, promote
b
/ read, execute
2
XP2 X
X
RX
1
XP1
XP1
X
RX
0
XP0
XP0
XP0
RX
a. RSC.pl, for RSE fills and spills; PSR.cpl for all other accesses.
b. User execute only pages can be enforced by setting PL to 3.
Table 4-4.
Page Access Rights (Continued)
TLB.ar
TLB.pl
Privilege Level
a
Description
3
2
1
0
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...