Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 824 / 1898

2:576 Volume 2, Part 2: Memory Management
For a long format VHPT, additional steps are required to load bytes 16-23 of the VHPT
entry and check for the correct tag; see
Section 5.4.1 for more details.
A separate structure other than the VHPT may be used to back VHPT translations, in
which case the handler would not use the thash instruction to generate the address of
the translation mapping the VHPT entry corresponding to the original faulting address.
Instead, the handler would use the operating system’s own mechanism for finding VHPT
back-mappings. Other schemes for handling VHPT misses are also possible, but are
beyond the scope of this document.
5.4.3 Alternate Data/Instruction TLB Miss Vectors
These faults are raised when an instruction or data reference misses the processor’s
TLBs and the VHPT walker is not enabled for the faulting address, i.e. TLB misses are
handled entirely in software. Operating systems which do not wish to use the VHPT
walker can disable the walker and use these fault vectors for software TLB fill handlers.
The OS may also choose to enable the walker on a per-region basis and use these
vectors to handle misses in regions where the walker is disabled.
Upon entry to these fault handlers, the IFA and ITIR registers are initialized by the
hardware as follows:
• ITIR – contains the default translation information for the reference which raised
the fault (i.e. for the virtual address contained in IFA). The access key field is set to
the region ID from the RR corresponding to the faulting address. The page size field
is set to the preferred page size (RR.ps) from the RR corresponding to the faulting
address.
• IFA – the virtual address of the bundle (for instruction faults) or data reference (for
data faults) which missed the TLB.
The OS needs to lookup the PTE for the faulting address in the OS page table, convert it
to the architected insertion format (see
Section 4.1.1.5, “Translation Insertion
Format” ), and insert it into the TLB. The mechanism used to handle these faults is OS
specific and is beyond the scope of this document.
5.4.4 Data Nested TLB Vector
To enable efficient handling of software TLB fills, the Itanium architecture provides a
dedicated Data Nested TLB fault vector. The Data Nested TLB fault handler is intended
to be used by the Data TLB fault handler, which allows the OS to page the page tables
themselves. When PSR.ic is 0, any data reference that misses the TLB and would
normally raise a Data TLB Miss fault (e.g. a load performed by the Data TLB fault
handler to the page tables) will vector to the Data Nested TLB fault handler instead.
Because IFA is not updated when PSR.ic is 0, the Data Nested TLB fault handler must
get the faulting address from the general register used as the load address in the Data
TLB fault handler
1
. Unlike other nested interruptions, the hardware does not update
ISR when a Data Nested TLB fault is delivered.
1. This requires a register usage convention between all TLB miss handlers and the Data Nested TLB
miss handler.