Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 821 / 1898

Volume 2, Part 2: Memory Management 2:573
5.3.2 Long Format
The long format VHPT is organized as a hash table which contains a subset of all
translation entries. The long format VHPT entries contain a 8-byte field that is ignored
by the VHPT walker and can be used by the operating system to link VHPT entries to
software-walkable hash collision chains if it uses the VHPT as its primary page table.
The size of the long format VHPT is usually kept small enough to keep a mapping for it
in one of the translation registers (TRs), so it is not necessary to handle VHPT
translation faults.
The long format hash algorithm is based on the per-region preferred page size, but a
translation for a larger page can still be entered into the VHPT by subdividing the large
page into multiple smaller pages with the preferred page size and placing an entry for
the large page at all VHPT locations that correspond to the smaller pages.
5.3.3 VHPT Updates
Visibility of VHPT updates to a VHPT walker on another processor follows the rules
outlined in
Section 4.1.7, “VHPT Environment” on page 2:67 . Since a global TLB purge
has release semantics, prior modifications to the VHPT will be visible to operations that
occur after the TLB purge operation.
Atomic updates to short format VHPT entries can easily be done through 8-byte stores.
For atomic updates of long format VHPT entries, the “ti” flag in bit 63 of the tag field
can be utilized as follows:
• Set the “ti” bit to 1.
• Issue a memory fence.
• Update the entry.
• Clear the “ti” bit through a store with release semantics.
5.4 TLB Miss Handlers
The Itanium architecture enables lightweight TLB fault handlers by providing individual
entry points for different excepting conditions and by pre-setting the translation
insertion registers for the various types of TLB faults. The following subsections list the
typical steps for resolving each kind of fault.
5.4.1 Data/Instruction TLB Miss Vectors
These faults occur when the data or instruction TLB required for a data access or
instruction fetch is not found in the processor TLBs, the VHPT walker is enabled, and:
• Either the VHPT walker aborted the walk (for any reason and at any time), or
• The VHPT walker found the translation but the insert failed (due to tag mismatch in
the long format or badly formed PTE), or
• The walker is not implemented on this processor.
There is a separate vector for each fault type (data and instruction).