Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 446 / 1898

2:198 Volume 2, Part 1: Interruption Vector Descriptions
Name
Speculation vector (0x5700)
Cause A
chk.a
,
chk.s
, or
fchkf
instruction needs to branch to recovery code, and the
branching behavior is unimplemented by the processor. This fault cannot be raised by
IA-32 instructions.
Interruptions on this vector:
Speculative Operation fault
Parameters IIP, IPSR, IIPA, IFS – are defined; refer to page 2:165 for a detailed description.
IIM – contains the immediate value from the
chk.s
,
chk.a
, or
fchkf
instruction.
IIB0, IIB1 – If implemented, the IIB registers contain the instruction bundle pointed to
by IIP. Please refer to
Section 3.3.5.10, “Interruption Instruction Bundle Registers
(IIB0-1 – CR26, 27)” on page 2:42 for details on the IIB registers.
ISR – The ISR.ei bits are set to indicate which instruction caused the exception. The
type of instruction which caused the fault is encoded in the lower four bits of the
ISR.code field.
• If ISR.code{3:0} = 0:
chk.a
general register speculation fault.
• If ISR.code{3:0} = 1:
chk.s
general register speculation fault.
• If ISR.code{3:0} = 2:
chk.a
floating-point speculation fault.
• If ISR.code{3:0} = 3:
chk.s
floating-point speculation fault.
• If ISR.code{3:0} = 4:
fchkf
fault.
The defined ISR bits are specified below.
Notes The Speculative Operation fault handler is required to perform the following steps:
1. Read the predicates and the IIM, IIP, IPSR, and ISR control registers, into scratch
bank 0 general registers.
2. Copy the IIP value to IIPA.
3. Sign-extend the IIM value (from 21 bits to 64), shift it left by 4 bits, add it to the
IIP value, and write this value back into IIP.
4. Set the IPSR.ri field to 0.
5. Check whether either IPSR.tb (Taken Branch trap) or IPSR.ss (Single Step
enable) is 1. If not, emulation is complete, so restore the predicates and
rfi
. If
so, then the check instruction would have taken one of these traps instead of
branching to its target, so this handler needs to branch directly to the appropriate
trap handler instead of performing the
rfi
(see steps 6 and 7).
6. If IPSR.tb was 1, then update ISR.code with its tb bit set to 1 and its ss bit also
set to 1 if IPSR.ss was 1, and all other bits 0. Restore the predicates, execute a
srlz.d
, and branch to the taken branch vector (IVT offset 0x5f00).
7. If IPSR.ss was 1 (but not IPSR.tb), then update ISR.code with its ss bit set to 1,
and all other bits 0. Restore the predicates, execute a
srlz.d
, and branch to the
single step vector (IVT offset 0x6000).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 code{3:0}
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
0 0 ei 0 ni 0 0 0 0 0 0 0