Volume 2, Part 1: Interruption Vector Descriptions
2:165
Interruption Vector Descriptions
8
describes the interruption mechanism and programming model for the
Itanium architecture. This chapter describes the IVA-based interruption handlers.
“Interruption Vector Descriptions”
describes all the Itanium IVA-based interruption
vectors and
“IA-32 Interruption Vector Definitions”
describes all of the IA-32 interrupt
vectors. PAL-based interruptions are described in
Chapter 11, “Processor Abstraction
Note that unless otherwise noted, references to “interruption” in this chapter
refer to IVA-based interruptions. See
“Interruption Definitions” on page 2:95
.
8.1
Interruption Vector Descriptions
The section lists all the Itanium interruption vectors. It describes the interruption
vectors and the parameters that are defined when the vector is entered.
If an interruption is independent of the executing instruction set (including IA-32), such
as an external interrupt or TLB fault, common Itanium interruption vectors are used.
For exceptions and intercept conditions that are specific to the IA-32 instruction set
three IA-32 specific vectors are used; IA_32_Exception, IA_32_Interrupt, and
IA_32_Intercept.
defines which interruption resources are written, are left unmodified, or are
undefined for each interruption vector. The individual vector descriptions below list
interruption-specific resources for each vector.
See
“IVA-based Interruption Handling” on page 2:101
for details on how the processor
handles an interruption. See
“Interruption Control Registers” on page 2:36
for the
definition of bit fields within the interruption resources.
8.2
ISR Settings
For each of the interruption vectors, a figure depicts the ISR setting. These figures
show the value that hardware writes into the ISR for the corresponding interruption.
provides an overview of ISR settings for all of the interruption vectors.
For some of the vectors, certain bits will always be 0 (or 1) simply because no
instruction that would set that bit differently can ever end up on that vector. For
example, ISR.sp is always 0 in the Break Instruction vector because ISR.sp is only set
by speculative loads, and speculative loads can never take a Break Instruction fault.
After interruption from the IA-32 instruction set, the following ISR bits will always be
zero: ISR.ni, ISR.na, ISR.sp, ISR.rs, ISR.ir, ISR.ei, and ISR.ed.
ISR.code settings for non-access instructions are described in
and Interruptions” on page 2:103
.
provides an overview of ISR.code field on all Itanium traps.
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...