Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 351 / 1898

Volume 2, Part 1: Interruptions 2:103
registers, overlapping GR16 to GR31. Which set of physical registers are accessed
through GR16 to GR31 is determined by the PSR.bn bit. On an interruption this bit is
forced to zero allowing access to the alternate set of 16 registers which can be used as
scratch space or to hold predetermined values. Software can return to the original set
of 16 GRs by setting the PSR.bn bit to one with
bsw
instruction. The rfi instruction may
also restore the PSR.bn bit to the value at the time of the interruption which is held in
the IPSR. Eight additional registers (KR0-KR7) can be used to hold latency critical
information for a handler. These application registers (KR0-KR7) can be read but not
written by non-privileged code.
When the processor handles an interruption event the current stack frame remains
unchanged and the IFS valid bit is cleared. The remaining contents of IFS are
undefined. While the interruption handler is running, the register stack engine (RSE)
may spill/fill registers to/from the backing store if eager RSE stores/loads are enabled.
The RSE will not load or store registers in the current frame (except as required on a
br.ret
or
rfi
in order to load the contents of the frame before continuing execution).
For most low-level interruptions the current frame will not be modified.
High-performance interruption handlers will not need to perform any register stack
manipulation. For example, a TLB miss handler does not need access to any registers in
the interrupted frame. An
rfi
instruction after an interruption and before a
cover
operation will also leave the frame marker unchanged (desired behavior for a low-level
interruption handler). When an interruption handler falls off the fast path it is required
to issue a
cover
instruction so that the interrupted frame can become part of backing
store. See “Switch from Interrupted Context” on page 2:148. .
It may be desirable to emulate a faulting instruction in the interruption handler and
rfi
back to the next sequential instruction rather than resuming at the faulting instruction.
Some Itanium instructions can be emulated without having to read the bundle from
memory, through knowledge of the vector, software convention, and information from
the ISR (e.g., emulation of
tpa
). However, most Itanium instructions will require
reading the bundle from memory and decoding the operation (e.g., an unaligned load).
To correctly emulate an unaligned load, the bundle is read from memory using the
value in the IIP which contains the bundle address. The instruction within the bundle
that caused the interruption is determined by the ISR.ei field. Once the operation is
decoded and emulation completes, the effect of the faulting instruction must be
nullified when control is returned to the point of the fault.
An Itanium instruction is skipped by adjusting PSR.ri and possibly IIP prior to
performing the
rfi
to the interrupted bundle. This is done by incrementing IPSR.ri by
the number of slots this instruction occupies (usually 1). If the resulting IPSR.ri is 3,
then reset IPSR.ri to 0 and advance IIP by 1 bundle (16 bytes). Emulating X-unit
instructions requires setting IPSR.ri to 0 and setting IIP to the next bundle (X-unit
instructions take up two instruction slots). IPSR, IIP, and IFS.pfm (if valid) will be
restored on an
rfi
to the PSR, IP, and CFM registers.
5.5.2 Non-access Instructions and Interruptions
The non-access Itanium instructions are:
fc
,
fc.i
,
lfetch
,
probe
,
probe.fault
,
tpa
,
and
tak
. These instructions reference the TLB but do not directly read or write memory.
They are distinguished from normal load/store instructions since an operating system
may wish to handle an interruption raised by a non-access instruction differently.