2:36
Volume 2, Part 1: System State and Programming Model
3.3.5
Interruption Control Registers
Registers CR16 - CR27 record information at the time of an interruption (including from
the IA-32 instruction set) and are used by handlers to process the interruption.
The interruption control registers can only be read or written while PSR.ic is 0;
otherwise, an Illegal Operation fault is raised. These registers are only guaranteed to
retain their values when PSR.ic is 0. When PSR.ic is 1, the processor does not preserve
their contents.
The contents of the interruption control registers are defined only when the PSR.ic bit is
cleared by an interruption. If the PSR.ic bit is explicitly cleared (e.g., by using
rsm
, or
mov to PSR), then the contents of these registers are undefined. If the PSR.ic bit is
explicitly set (e.g., by using
ssm
, or mov to PSR), then the contents of these registers
are undefined until the PSR.ic bit has been serialized and an interruption occurs.
IIPA has special behavior in case of an
rfi
to a fault. Refer to
Previous Address (IIPA – CR22)” on page 2:40
3.3.5.1
Interruption Processor Status Register (IPSR – CR16)
On an interruption and if PSR.ic is 1, the IPSR receives the value of the PSR. The IPSR,
IIP and IFS are used to restore processor state on a Return From Interruption (
rfi
).
The IPSR has the same format as PSR, see
“Processor Status Register (PSR)” on
for details.
3.3.5.2
Interruption Status Register (ISR – CR17)
The ISR receives information related to the nature of the interruption, and is written by
the processor on all interruption events regardless of the state of PSR.ic, except for
Data Nested TLB faults. The ISR contains information about the excepting instruction
and its properties such as whether it was doing a read, write, execute, speculative, or
non-access operation, see
and
. Multiple bits may be concurrently
set in the ISR, for example, a faulting semaphore operation will set both ISR.r and
ISR.w, and faults on speculative loads will set ISR.sp and ISR.r. Additional fault- or
trap-specific information is available in ISR.code and ISR.vector. Refer to
for complete definition of the ISR field settings.
Figure 3-9.
Interruption Status Register (ISR – CR17)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
rv
vector
code
8
8
16
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
rv
ed
ei
so ni ir rs sp na r w x
20
1
2
1
1
1
1
1
1
1
1
1
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...