1:184
Volume 1, Part 2: Software Pipelining and Loop Support
the loop has the same schedule. It is likely that software pipelining algorithms other
than modulo scheduling could benefit from the loop support features. Therefore the
examples in this chapter are discussed in terms of software pipelining rather than
modulo scheduling.
Software pipelined loops have three phases: prolog, kernel, and epilog, as shown
below:
1 2 3 4 5 Phase
----------------------------------------------------
ld4
ld4
Prolog
add
ld4
----------------------------------------------------
st4 add
ld4 Kernel
st4 add
ld4
------------------------------------------------------
st4 add
st4 add Epilog
st4
During the prolog phase, a new loop iteration is started every II cycles (every cycle for
the above example) to fill the pipeline. During the first cycle of the prolog, stage 1 of
the first iteration executes. During the second cycle, stage 1 of the second iteration and
stage 2 of the first iteration execute, etc. By the start of the kernel phase, the pipeline
is full. Stage 1 of the fourth iteration, stage 2 of the third iteration, stage 3 of the
second iteration, and stage 4 of the first iteration execute. During the kernel phase, a
new loop iteration is started, and another is completed every II cycles. During the
epilog phase, no new iterations are started, but the iterations already in progress are
completed, draining the pipeline. In the above example, iterations 3-5 are completed
during the epilog phase.
The software pipeline is coded as a loop that is very different from the original source
code loop. To avoid confusion when discussing loops and loop iterations, we use the
term
source loop
and
source iteration
to refer back to the original source code loop, and
the term
kernel loop
and
kernel iteration
to refer to the loop that implements the
software pipeline.
In the above example, the load from the second source iteration is issued before result
of the first load is consumed. Thus, in many cases, loads from successive iterations of
the loop must target different registers to avoid overwriting existing live values. In
traditional architectures, this requires unrolling of the kernel loop and software
renaming of the registers, resulting in code expansion. Furthermore, in traditional
architectures, separate blocks of code are generated for the prolog, kernel, and epilog
phases, resulting in additional code expansion.
5.4
Loop Support Features in the Intel
®
Itanium
®
Architecture
The code expansion that results from loop optimizations (such as software pipelining
and loop unrolling) on traditional architectures can increase the number of instruction
cache misses, thus reducing overall performance. The loop support features in the
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...