Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 819 / 1898

Volume 2, Part 2: Memory Management 2:571
The
ptc.ga
variant of the global purge instruction behaves just like the
ptc.g
variant,
but it also removes any ALAT entries which fall into the address range specified by the
global shootdown from all remote processors’ ALATs. The
ptc.ga
variant is intended to
be used whenever a translation is remapped to a different physical address to ensure
that any stale ALAT entries are invalidated. Note that the
ptc.ga
is not guaranteed to
affect the issuing processor's ALAT; processor implementations may optionally remove
matching entries from the local ALAT, therefore software must perform a local ALAT
invalidation via the
invala
instruction on the processor issuing the
ptc.ga
to ensure
the local ALAT is coherent.
Note that processors based on the Itanium architecture may support one or more
implementation-dependent purge sizes; some implementations may include a
region-wide purge. The PAL_VM_PAGE_SIZE firmware call returns the supported page
sizes for purges for a particular processor implementation. Refer to
Section 11.10.1,
“PAL Procedure Summary” for details. When software wishes to purge an address range
that is much larger than the largest supported purge size from all TCs in the coherence
domain, performance may be enhanced by issuing inter-processor interrupts to all
processors and using the
ptc.e
loop described in Section 5.2.2.2.2 on each processor,
instead of issuing many
ptc.g
instructions from one processor.
ptc.g
instructions do not apply to processors outside the coherence domain of the
processor issuing the
ptc.g
instruction. Systems with multiple coherence domains must
use a platform-specific method for maintaining TLB coherence across coherence
domains.
5.3 Virtual Hash Page Table
The Itanium architecture defines a data structure that allows for the insertion of TLB
entries by a hardware mechanism. The data structure is called the “virtual hash page
table” (VHPT) and the hardware mechanism is called the VHPT walker.
Unlike the IA-32 page tables, the Itanium VHPT itself is virtually mapped, i.e. VHPT
walker references can take TLB faults themselves. Virtual mapping of the page tables is
needed because the page tables for 2
64
address space are quite large and typically do
not fit into physical memory.
The Itanium architecture prescribes the format of a leaf-node page table entry (PTE)
seen by the VHPT walker, but does not impose an OS page table data structure itself. As
summarized in
Table 5-1 , the architecture support two different VHPT formats:
• Short format uses 8-byte PTEs, and is a linear page table. The short format VHPT
does not contain protection key information (there are not enough PTE bits for
that). Short format is a per-region linear page table, i.e. the PTEs and hash function
are independent of the RID. The short format prefers use of a self-mapped page
table. The short format VHPT is an efficient representation for address spaces that
contain only a few large clusters of pages, like the text, data, and stack segments
of applications running on a MAS operating system.
• Long format uses 32-byte PTEs, and is a hashed page table. The hash function
embedded in hardware. The long format supports protection keys and the use of
multiple page sizes in a region. The long format hash and tag functions incorporate
the RID, and allows multiple address space translations to be present in the same
VHPT. The long format is expected to be used either as a cache of the real OS page