Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 387 / 1898

Volume 2, Part 1: Register Stack Engine 2:139
6.5 RSE Control
The RSE can be controlled at all privilege levels by means of three instructions (
cover
,
flushrs
, and
loadrs
) and by accessing four application registers (mov to/from RSC,
BSP, BSPSTORE and RNAT). This section first presents each of the RSE application
registers, and then discusses the three RSE control instructions.
6.5.1 Register Stack Configuration Register
The layout of the Register Stack Configuration application register (RSC) is defined in
Section 3.1.8.2, “Register Stack Configuration Register (RSC – AR 16)” on page 1:29 .
This section describes the semantics of the mode, the privilege level and the byte order
fields of the RSC. The loadrs field is described as part of the
loadrs
instruction in
Section 6.5.4, “RSE Control Instructions” on page 2:142 .
RSE Mode : Two mode bits in the RSC register determine when the RSE generates
register spill or fill operations. When both mode bits are zero (enforced lazy mode) the
RSE issues only mandatory loads and stores (when an
alloc
,
br.ret
,
flushrs
or
rfi
instruction requires registers to be spilled or filled). Bit 0 of the RSC.mode field enables
eager RSE stores and bit 1 enables eager RSE loads.
Table 6-3 defines all four possible
RSE modes. Please see the processor-specific documentation for further information on
the RSE modes implemented by the Itanium processor.
The algorithm that decides whether and when to speculatively perform eager register
spill or fill operations is implementation dependent. Software may not make any
assumptions about the RSE load/store behavior when the RSC.mode is non-zero.
Furthermore, access to the BSPSTORE and RNAT application registers and the
execution of the
loadrs
instructions require RSC.mode to be zero (enforced lazy
mode). If
loadrs
, move to/from BSPSTORE or move to/from RNAT are executed when
RSC.mode is non-zero an Illegal operation fault is raised. Eager spill/fill of the RNAT
register to/from the backing store is only permitted if the RSE is in store/load intensive
or eager mode. In enforced lazy mode, the RSE may spill/fill the RNAT register only if a
subsequent mandatory register spill/fill is required.
RSE Privilege Level: When address translation is enabled (PSR.rt is one), the RSE
operates at a privilege level defined by two privilege level bits in the Register Stack
Configuration register (RSC.pl). All privilege level checks for RSE virtual accesses are
performed using the privilege level in RSC.pl. When the RSC is written, the privilege
level bits are clipped to the current privilege level of the process, i.e., the numerical
maximum of the current privilege level and the privilege level in the source register is
written to RSC.pl.
Table 6-3. RSE Modes (RSC.mode)
Mode RSE Loads RSE Stores RSC.mode
Enforced Lazy Mandatory only Mandatory only 00
Store Intensive Mandatory only Eager and Mandatory 01
Load Intensive Eager and Mandatory Mandatory only 10
Eager Eager and Mandatory Eager and Mandatory 11