Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 390 / 1898

2:142 Volume 2, Part 1: Register Stack Engine
6.5.4 RSE Control Instructions
This section describes the RSE control instructions:
cover
,
flushrs
and
loadrs
. The
effects of the three RSE control instructions on the RSE state are summarized in
Table 6-5 .
The
cover
instruction adds all registers in the current frame to the dirty partition, and
allocates a zero-size current frame. As a result AR[BSP] is updated.
cover
clears the
register rename base fields in the current frame marker CFM. If PSR.ic is zero, the
original value of CFM is copied into CR[IFS].ifm and CR[IFS].v is set to one. The
cover
instruction must the last instruction in an instruction group; otherwise, operation is
undefined.
The
flushrs
instruction spills all dirty registers to the backing store. When it
completes, RSE.ndirty is defined to be zero, and BSPSTORE equals BSP. Since
flushrs
may cause RSE stores, the RNAT application register is updated. A
flushrs
instruction
must be the first instruction in an instruction group otherwise the results are undefined.
The
loadrs
instruction ensures that a specified portion of the backing store below the
current BSP is present in the physical stacked registers. The size of the backing store
section is specified in the
loadrs
field of the RSC application register (AR[RSC].loadrs).
After loadrs completes, all registers and NaT collections between the current BSP and
the tear-point (BSP-(RSC.loadrs{13:3} << 3)), and no more than that, are guaranteed
to be present and marked as dirty in the stacked physical registers. When
loadrs
completes BSPSTORE and RSE.BspLoad are defined to be equal to the backing store
tear-point address. All other physical stacked registers are marked invalid.
• If the tear-point specifies an address below RSE.BspLoad, the RSE issues
mandatory loads to restore registers and NaT collections. All registers between the
current BSP and the tear-point are marked dirty.
• If the RSE has already loaded registers beyond the tear-point when the
loadrs
instruction executes, the RSE marks clean registers below the tear-point as invalid
and marks clean registers above the tear-point as dirty.
• If the tear-point specifies an address greater than BSPSTORE, the RSE marks clean
and dirty registers below the tear-point as invalid (in this case dirty registers are
lost).
Table 6-4. Backing Store Pointer Application Registers
Affected State
Instruction
Read BSP
mov r
1
=AR[BSP]
Read BSPSTORE
mov r
1
=AR[BSPSTORE]
Write BSPSTORE
a
mov AR[BSPSTORE]= r
2
a. Writing to AR[BSPSTORE] has undefined behavior with an incomplete frame. See “RSE Behavior with an
Incomplete Register Frame” on page 2:146.
GR[
r
1
] AR[BSP] AR[BSPSTORE] N/A
AR[BSP]{63:3} Unchanged Unchanged (GR[
r
2
]{63:3} + RSE.ndirty) +
((GR[
r
2
]{8:3} + RSE.ndirty)/63)
AR[BSPSTORE]{63:3} Unchanged Unchanged GR[
r
2
]{63:3}
RSE.BspLoad {63:3} Unchanged Unchanged GR[
r
2
]{63:3}
AR[RNAT] Unchanged Unchanged UNDEFINED
RSE.RNATBitIndex Unchanged Unchanged GR[ r
2
]{8:3}