Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 394 / 1898

2:146 Volume 2, Part 1: Register Stack Engine
6.7 RSE Behavior on Interruptions
When the processor raises an interruption, the current register stack frame remains
unchanged. If PSR.ic is one, the valid bit in the Interruption Function State register
(IFS.v) is cleared. When the IFS.v bit is clear, the contents of the interruption frame
marker field (IFS.ifm) are undefined.
While an interruption handler is running and the RSE is in store/load intensive or eager
mode, the RSE continues spilling/filling registers to/from the backing store on behalf of
the interrupted context as long as the registers are not part of the current frame as
defined by CFM.
A sequence of mandatory RSE loads or stores (from
alloc
,
br.ret
,
flushrs
,
loadrs
and
rfi
) can be interrupted by an external interrupt.
When PSR.ic is 0, faults taken on mandatory RSE operations may not be recoverable.
6.8 RSE Behavior with an Incomplete Register Frame
The current register frame is considered incomplete when one of the mandatory RSE
loads after a br.ret or a rfi faults, leaving BSPSTORE pointing to a location above BSP
(i.e., RSE.ndirty_words is negative). The frame becomes complete when
RSE.ndirty_words becomes non-negative, either by executing a cover instruction, or by
handling the fault and completing the original sequence of mandatory RSE loads.
When the current frame is incomplete the following instructions have undefined
behavior:
alloc
,
br.call
,
brl.call
,
br.ret
,
flushrs
,
loadrs
, and move to
BSPSTORE. Software must guarantee that the current frame is complete before
executing these instructions.
6.9 RSE and ALAT Interaction
The ALAT (see “Data Speculation” on page 1:63 ) uses physical register addresses to
track advanced loads. RSE.BOF may only change as the result of a
br.call
(by
CFM.sol),
cover
(by CFM.sof),
br.ret
(by AR[PFM].sol) or
rfi
(by CR[IFS].ifm.sof
when CR[IFS].v =1). This ensures, for ALAT invalidation purposes, that hardware does
not update virtual to physical register address mapping, unless explicitly instructed to
do so by software.
When software performs backing store switches that could cause program values to be
placed in different physical registers, then the ALAT must be explicitly invalidated with
the
invala
instruction. Typically this happens as part of a process or thread context
switch, longjmp or call stack unwind, when software re-writes AR[BSPSTORE], but
cannot guarantee that RSE.BOF was preserved.
A stacked register is said to be deallocated when an
alloc
,
br.ret
, or
rfi
instruction
changes the top of the current frame such that the register is no longer part of the
current frame. Once a stacked register is deallocated, its value, its corresponding NaT
bit, and its ALAT state are undefined. If that register is subsequently made part of the