Volume 2, Part 1: Register Stack Engine
2:143
By specifying a zero RSC.loadrs value
loadrs
can be used to invalidate all stacked
registers outside the current frame.
loadrs
causes the contents of the RNAT register to
become undefined. The NaT collection index is set to bits {8:3} of the new BSPSTORE.
A
loadrs
instruction must be the first instruction in an instruction group otherwise the
results are undefined. The following conditions cause
loadrs
to raise an Illegal
Operation fault:
• If RSC.mode is non-zero.
• If both CFM.sof and RSC.loadrs are non-zero.
• If RSC.loadrs specifies more words to be loaded than will fit in the stacked physical
register file (RSE.N_STACKED_PHYS).
6.5.5
Bad PFS used by Branch Return
On a
br.ret
, if the PFS application register defines an output area which is larger than
the number of implemented stacked registers minus the size of dirty partition
((AR[PFS].sof - AR[PFS].sol) > (RSE.N_STACKED_PHYS - RSE.ndirty)), the return will
not restore CFM with AR[PFS].pfm (normal behavior); instead, the return sets all fields
in the CFM (of the procedure being returned to) to zero.
Typical procedure call and return sequences that preserve PFS values and that do not
use
cover
or
loadrs
instructions will not encounter this situation.
The RSE will detect the above condition on a
br.ret
, and update its state as follows:
• The register rename base (RSE.BOF), AR[BSP], and AR[BSPSTORE] are updated as
required by the return.
Table 6-5.
RSE Control Instructions
Affected State
Instruction
cover
flushrs
a
a. These instructions have undefined behavior with an incomplete frame.
See “RSE Behavior with an Incomplete
Register Frame” on page 2:146.
loadrs
AR[BSP]{63:3}
AR[BSP]{63:3}+ CFM.sof +
(AR[BSP]{8:3} + CFM.sof)/63
Unchanged
Unchanged
AR[BSPSTORE]{63:3}
Unchanged
AR[BSP]{63:3}
AR[BSP]{63:3} -
AR[RSC].loadrs{13:3}
RSE.BspLoad{63:3}
Unchanged
Model specific
b
b. In general, eager RSE implementations will preserve RSE.BspLoad during a
flushrs
. Lazy RSE
implementations may set RSE.BspLoad to AR[BSPSTORE] after flushrs completes or faults.
AR[BSP]{63:3} -
AR[RSC].loadrs{13:3}
AR[RNAT]
Unchanged
Updated
UNDEFINED
RSE.RNATBitIndex
Unchanged
AR[BSPSTORE]{8:3}
AR[BSPSTORE]{8:3}
CR[IFS]
if (PSR.ic == 0) {
CR[IFS].ifm = CFM
CR[IFS].v = 1}
Unchanged
Unchanged
CFM
CFM.sof = 0
CFM.sol = 0
CFM.sor = 0
CFM.rrb.gr = 0
CFM.rrb.fr = 0
CFM.rrb.pr = 0
Unchanged
Unchanged
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...