Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 354 / 1898

2:106 Volume 2, Part 1: Interruptions
Aborts, external interrupts, RSE or instruction-fetch-related faults that happen to occur
on a speculative load are always raised (since they are not related to the speculative
load instruction). Illegal Operation faults and Disabled Floating-point Register faults
that occur on a speculative load are always raised.
Processing of exception conditions for speculative and speculative advanced loads is
done in three stages: qualification, deferral and prioritization.
During the execution of a load instruction, multiple exception conditions may be
detected simultaneously. For non-speculative loads these exception conditions are
prioritized and only the highest priority one raises a fault. For speculative loads,
however, some exception conditions may be deferred. As a result, it is possible for
lower priority exceptions, which are not also deferred, to raise a fault. For some
exception conditions, though, other lower priority conditions are meaningless, and are
said to be qualified, or precluded. Exception qualification is described in
Table 5-3 .
After exception conditions are detected and qualified, the remaining exception
conditions are checked for deferral. Deferral occurs after fault qualification and
determines which memory access exceptions raised by speculative loads are
automatically deferred by hardware.
Table 5-3. Exception Qualification
Exception Condition Precluded by Concurrent Exception Condition
Register NaT Consumption
(NaT’ed address) none
Unimplemented Data Address Register NaT Consumption
Alternate Data TLB Register NaT Consumption Unimplemented Data Address
VHPT data Register NaT Consumption Unimplemented Data Address
Data TLB Register NaT Consumption Unimplemented Data Address
Data Page Not Present Register NaT Consumption
Unimplemented Data Address
VHPT data Data TLB
Alternate Data TLB
Data NaT Page Consumption Register NaT Consumption
Unimplemented Data Address
VHPT data Data TLB
Alternate Data TLB
Data Page Not Present
Data Key Miss Register NaT Consumption
Unimplemented Data Address
VHPT data Data TLB
Alternate Data TLB
Data Page Not Present
Data Key Permission Register NaT Consumption
Unimplemented Data Address
VHPT data
Data TLB Alternate Data TLB
Data Page Not Present
Data Key Miss
Data Access Rights Register NaT Consumption
Unimplemented Data Address
VHPT data Data TLB
Alternate Data TLB
Data Page Not Present
Data Access Bit Register NaT Consumption
Unimplemented Data Address
VHPT data Data TLB
Alternate Data TLB
Data Page Not Present
Data Debug Register NaT Consumption Unimplemented Data Address
Unaligned Data Reference Register NaT Consumption Unimplemented Data Address
Unsupported Data Reference Register NaT Consumption
Unimplemented Data Address
VHPT data Data TLB
Alternate Data TLB
Data Page Not Present