Volume 3: Instruction Reference
3:35
chk
chk — Speculation Check
Format:
(
qp
) chk.s
r
2
,
target
25
pseudo-op
(
qp
) chk.s.i
r
2
,
target
25
control_form, i_unit_form, gr_form
(
qp
) chk.s.m
r
2
,
target
25
control_form, m_unit_form, gr_form
(
qp
) chk.s
f
2
,
target
25
control_form, fr_form
(
qp
) chk.a.
aclr r
1
,
target
25
data_form, gr_form
(
qp
) chk.a.
aclr f
1
,
target
25
data_form, fr_form
Description:
The result of a control- or data-speculative calculation is checked for success or failure.
If the check fails, a branch to
target
25
is taken.
In the control_form, success is determined by a NaT indication for the source register.
If the NaT bit corresponding to GR
r
2
is 1 (in the gr_form), or FR
f
2
contains a NaTVal (in
the fr_form), the check fails.
In the data_form, success is determined by the ALAT. The ALAT is queried using the
general register specifier
r
1
(in the gr_form), or the floating-point register specifier
f
1
(in the fr_form). If no ALAT entry matches, the check fails. An implementation may
optionally cause the check to fail independent of whether an ALAT entry matches. A
chk.a
with general register specifier r0 or floating-point register specifiers f0 or f1
always fails.
The
target
25
operand, in assembly, specifies a label to branch to. This is encoded in the
instruction as a signed immediate displacement (
imm
21
) between the target bundle and
the bundle containing this instruction (
imm
21
=
target
25
- IP >> 4).
The branching behavior of this instruction can be optionally unimplemented. If the
instruction would have branched, and the branching behavior is not implemented, then
a Speculative Operation fault is taken and the value specified by
imm
21
is zero-extended
and placed in the Interruption Immediate control register (IIM). The fault handler
emulates the branch by sign-extending the IIM value, adding it to IIP and returning.
The control_form of this instruction for checking general registers can be encoded on
either an I-unit or an M-unit. The pseudo-op can be used if the unit type to execute on
is unimportant.
For the data_form, if an ALAT entry matches, the matching ALAT entry can be optionally
invalidated, based on the value of the
aclr
Note that if the
clr
value of the
aclr
completer is used and the check succeeds, the
matching ALAT entry is invalidated. However, if the check fails (which may happen even
if there is a matching ALAT entry), any matching ALAT entry may optionally be
invalidated, but this is not required. Recovery code for data speculation, therefore,
cannot rely on the absence of a matching ALAT entry.
Table 2-14.
ALAT Clear Completer
aclr
Completer
Effect on ALAT
clr
Invalidate matching ALAT entry
nc
Don’t invalidate
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...