Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 1383 / 1898

Volume 4: Base IA-32 Instruction Reference 4:81
6 PAE Physical Address Extension. Physical addresses greater than 32
bits are supported: extended page table entry formats, an extra level
in the page translation tables is defined, 2 Mbyte pages are supported
instead of 4 Mbyte pages if PAE bit is 1. The actual number of address
bits beyond 32 is not defined, and is implementation specific.
7 MCE Machine Check Exception. Exception 18 is defined for Machine
Checks, including CR4.MCE for controlling the feature. This feature
does not define the model-specific implementations of machine-check
error logging, reporting, and processor shutdowns. Machine Check
exception handlers may have to depend on processor version to do
model-specific processing of the exception, or test for the presence of
the Machine Check feature.
8 CX8 CMPXCHG8B Instruction. The compare-and-exchange 8 bytes (64
bits) instruction is supported (implicitly locked and atomic).
9 APIC APIC On-Chip. The processor contains an Advanced Programmable
Interrupt Controller (APIC), responding to memory mapped
commands in the physical address range FFFE0000H to FFFE0FFFH
(by default – some processors permit the APIC to be relocated).
10 Reserved Reserved.
11 SEP SYSENTER and SYSEXIT Instructions. The SYSENTER and
SYSEXIT and associated MSRs are supported.
12 MTRR Memory Type Range Registers. MTRRs are supported. The
MTRRcap MSR contains feature bits that describe what memory
types are supported, how many variable MTRRs are supported, and
whether fixed MTRRs are supported.
13 PGE PTE Global Bit. The global bit in page directory entries (PDEs) and
page table entries (PTEs) is supported, indicating TLB entries that are
common to different processes and need not be flushed. The
CR4.PGE bit controls this feature.
14 MCA Machine Check Architecture. The Machine Check Architecture,
which provides a compatible mechanism for error reporting is
supported. The MCG_CAP MSR contains feature bits describing how
many banks of error reporting MSRs are supported.
15 CMOV Conditional Move Instructions. The conditional move instruction
CMOV is supported. In addition, if x87 FPU is present as indicated by
the CPUID.FPU feature bit, then the FCOMI and FCMOV instructions
are supported.
16 PAT Page Attribute Table. Page Attribute Table is supported. This feature
augments the Memory Type Range Registers (MTRRs), allowing an
operating system to specify attributes of memory on a 4K granularity
through a linear address.
17 PSE-36 32-Bit Page Size Extension. Extended 4-MByte pages that are
capable of addressing physical memory beyond 4 GBytes are
supported. This feature indicates that the upper four bits of the
physical address of the 4-MByte page is encoded by bits 13-16 of the
page directory entry.
18 PSN Processor Serial Number. The processor supports the 96-bit
processor identification number feature and the feature is enabled.
19 CLFSH CLFLUSH Instruction. CLFLUSH Instruction is supported.
20 NX Execute Disable Bit.
21 DS Debug Store. The processor supports the ability to write debug
information into a memory resident buffer. This feature is used by the
branch trace store (BTS) and precise event-based sampling (PEBS)
facilities.
Table 2-5. Feature Flags Returned in EDX Register (Continued)
Bit Mnemonic Description