Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 436 / 1898

2:188 Volume 2, Part 1: Interruption Vector Descriptions
Name
Page Not Present vector (0x5000)
Cause The bundle or IA-32 instruction being executed resides on a page for which the P-bit
(TLB.p) in the instruction TLB entry is 0, or the data being referenced resides on a page
for which the P-bit in the data TLB entry is 0.
Interruptions on this vector:
IR Data Page Not Present fault
Instruction Page Not Present fault
Data Page Not Present fault
Parameters IIP, IPSR, IIPA, IFS – are defined; refer to page 2:165 for a detailed description.
ITIR – The ITIR contains default translation information for the address contained in the
IFA. The access key field within this register is set to the region id value from the
referenced region register.
The ITIR.ps field is set to the RR.ps field from the referenced
region register. All other fields are set to 0.
IIB0, IIB1 – If implemented, for Data Page Not Present faults, the IIB registers contain
the instruction bundle pointed to by IIP. The IIB registers are undefined for IR Data
Page Not Present and Instruction Page Not Present faults. Please refer to
Section 3.3.5.10, “Interruption Instruction Bundle Registers (IIB0-1 – CR26, 27)” on
page 2:42
for details on the IIB registers.
If the fault is due to a data page not present fault for both instruction and data original
references:
• IFA – The virtual address of the data being referenced.
• ISR – If the interruption was due to a non-access operation then the ISR.code bits
{3:0} are set to indicate the type of the non-access instruction; otherwise they are
set to 0. The value for the ISR bits depend on the type of access performed and are
specified below. For mandatory RSE fill or spill references, ISR.ed is always 0. For
IA-32 memory references, ISR.code, ed, ei, ni, ir, rs, sp and na bits are 0.
If the fault is due to an instruction page not present fault:
• IFA – The virtual address of the bundle or the 16 byte aligned IA-32 instruction
address zero extended to 64-bits.
• ISR – The ISR.ei bits are set to indicate which instruction caused the exception. The
defined ISR bits are specified below. For IA-32 memory references the ISR.ei and ni
bits are 0.
Notes This fault can only occur when PSR.it is 1 on an instruction reference, when PSR.dt is 1
on a load, store, semaphore, or non-access operation, or when PSR.rt is 1 on a RSE
mandatory load/store operation.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 code{3:0}
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
0 ed ei so ni ir rs sp na r w 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
0 0 ei 0 ni 0 0 0 0 0 0 1