Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 46 / 1898

Volume 1, Part 1: Execution Environment 1:35
CPUID register 4 provides general application-level information about processor
features. As shown in
Figure 3-12 , it is a set of flag bits used to indicate if a given
feature is supported in the processor model. When a bit is one the feature is supported;
when 0 the feature is not supported. The defined feature bits in the current architecture
are listed in
Table 3-8 . As new features are added (or removed) from future processor
models the presence (or removal) of new features will be indicated by new feature bits.
CPUID register 4 is logically split into two halves, both of which contain general feature
and capability information but which have different usage models and access
capabilities; this information reflects the status of any enabled or disabled features.
Both the upper and lower halves of CPUID register 4 are accessible through the move
indirect register instruction; depending on the implementation, the latency for this
access can be long and this access method is not appropriate for low-latency code
versioning using self-selection. In addition, the upper half of CPUID register 4 is also
accessible using the test feature instruction; the latency for this access is comparable
to that of the test bit instruction and this access method enables low-latency code
versioning using self selection.
This register does not contain IA-32 instruction set features. IA-32 instruction set
features can be acquired by the IA-32 cpuid instruction.
Table 3-7. CPUID Register 3 Fields
Field Bits Description
number 7:0 The index of the largest implemented CPUID register (one less than the number of
implemented CPUID registers). This value will be at least 4.
revision 15:8 Processor revision number. An 8-bit value that represents the revision or stepping
of this processor implementation within the processor model.
model 23:16 Processor model number. A unique 8-bit value representing the processor model
within the processor family.
family 31:24 Processor family number. A unique 8-bit value representing the processor family.
archrev 39:32 Architecture revision. An 8-bit value that represents the architecture revision
number that the processor implements.
rv 63:40 Reserved.
Figure 3-12. CPUID Register 4 – General Features/Capability Bits
63 34 33 32 31 4 3 2 1 0
rv x2 cz rv ru ao sd lb
30 1 1 28 1 1 1 1
Table 3-8. CPUID Register 4 Fields
Field Bits Description
lb 0 Processor implements the long branch (
brl
) instructions.
sd 1 Processor implements spontaneous deferral (see Section 5.5.5, “Deferral of
Speculative Load Faults” on page 2:105 ).
ao 2 Processor implements 16-byte atomic operations (see “ld — Load” , “st — Store” and
“cmpxchg — Compare and Exchange” instructions in Volume 3 ).
ru 3 Processor implements the Resource Utilization Counter (AR 45).
rv 31:4 Reserved.
cz 32 Processor implements the
clz
instruction (see “tf — Test Feature” instruction in
Volume 3 ).