Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 604 / 1898

2:356 Volume 2, Part 1: Processor Abstraction Layer
PAL_PROC_SET_FEATURES
a
18 Req. Static Phys. No Enable or disable configurable processor
features.
PAL_REGISTER_INFO 39 Req. Static Both No Return AR and CR register information.
PAL_RSE_INFO 19 Req. Static Both No Return RSE information.
PAL_SET_HW_POLICY
a
49 Opt. Static Both Dep. Set current hardware resource sharing policy.
PAL_VERSION 20 Req. Static Both No Return version of PAL code.
a. Calling this procedure may affect resources on multiple processors. Please refer to implementation-specific reference manuals
for details.
Table 11-51.PAL Machine Check Handling Procedures
Procedure Idx Class Conv. Mode Buffer Description
PAL_MC_CLEAR_LOG
a
a. Calling this procedure may affect resources on multiple processors. Please refer to implementation-specific reference manuals
for details.
21 Req. Static Both No Clear all error information from processor error
logging registers.
PAL_MC_DRAIN 22 Req. Static Both No Ensure that all operations that could cause an
MCA have completed.
PAL_MC_DYNAMIC_STATE 24 Opt. Static Both No Return Processor Dynamic State for logging by
SAL.
PAL_MC_ERROR_INFO 25 Req. Static Both No Return Processor Machine Check Information
and Processor Static State for logging by SAL.
PAL_MC_ERROR_INJECT
a
276 Opt. Stacked Both Dep. Injects the requested processor error or returns
information on the supported injection
capabilities for this particular processor
implementation.
PAL_MC_EXPECTED 23 Req. Static Phys. No Set/Reset Expected Machine Check Indicator.
PAL_MC_HW_TRACKING 51 Opt. Static Both Dep. Query which hardware structures are
performing hardware status tracking
PAL_MC_REGISTER_MEM 27 Req. Static Phys. No Register min-state save area with PAL for
machine checks and inits.
PAL_MC_RESUME 26 Req. Static Phys. No Restore minimal architected state and return to
interrupted process.
Table 11-52.PAL Power Information and Management Procedures
Procedure Idx Class Conv. Mode Buffer Description
PAL_GET_PSTATE 262 Opt. Stacked Both Dep. Returns information on the performance index
of the processor.
PAL_HALT 28 Opt. Static Phys No Enter the low-power HALT state or an
implementation-dependent low-power state.
PAL_HALT_INFO 257 Req. Stacked Both No Return the low power capabilities of the
processor.
PAL_HALT_LIGHT 29 Req. Static Both No Enter the low power LIGHT HALT state.
PAL_PSTATE_INFO 44 Opt. Static Both No Returns information about the P-states
supported by the processor.
PAL_SET_PSTATE
a
263 Opt. Stacked Both Dep. Request processor to enter power/performance
state.
PAL_SHUTDOWN 45 Opt. Static Phys Dep. Puts the processor in a low power state which
can be exited only by a reset event.
Table 11-50.PAL Processor Identification, Features, and Configuration Procedures
Procedure Idx Class Conv. Mode Buffer Description