3:180
Volume 3: Instruction Reference
mov indirect
mov — Move Indirect Register
Format:
(
qp
) mov
r
1
=
ireg
[
r
3
]
from_form
(
qp
) mov
ireg
[
r
3
] =
r
2
to_form
Description:
The source operand is copied to the destination register.
For move from indirect register, GR
r
3
is read and the value used as an index into the
register file specified by
ireg
(see
below). The indexed register is read and its
value is copied into GR
r
1
.
For move to indirect register, GR
r
3
is read and the value used as an index into the
register file specified by
ireg
. GR
r
2
is read and its value copied into the indexed register.
For all register files other than the region registers, bits {7:0} of GR
r
3
are used as the
index. For region registers, bits {63:61} are used. The remainder of the bits are
ignored.
Instruction and data breakpoint, performance monitor configuration, protection key,
and region registers can only be accessed at the most privileged level. Performance
monitor data registers can only be written at the most privileged level.
The CPU identification registers can only be read. There is no to_form of this
instruction.
For move to protection key register, the processor ensures uniqueness of protection
keys by checking new valid protection keys against all protection key registers. If any
matching keys are found, duplicate protection keys are invalidated.
Apart from the PMC and PMD register files, access of a non-existent register results in a
Reserved Register/Field fault. All accesses to the implementation-dependent portion of
PMC and PMD register files result in implementation dependent behavior but do not
fault.
Modifying a region register or a protection key register which is being used to translate:
• the executing instruction stream when PSR.it == 1, or
• the data space for an eager RSE reference when PSR.rt == 1
is an undefined operation.
Operation:
if (PR[
qp
]) {
if (
ireg
== RR_TYPE)
tmp_index = GR[
r
3
]{63:61};
else // all other register types
tmp_index = GR[
r
3
]{7:0};
Table 2-40.
Indirect Register File Mnemonics
ireg
Register
File
cpuid
Processor Identification Register
dbr
Data Breakpoint Register
ibr
Instruction Breakpoint Register
pkr
Protection Key Register
pmc
Performance Monitor Configuration Register
pmd
Performance Monitor Data Register
rr
Region Register
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...