Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 141 / 1898

1:130 Volume 1, Part 1: IA-32 Application Execution Model in an Intel
®
Itanium
®
System Environment
To avoid performance degradation, software programmers are strongly recommended
not to intermix IA-32 floating and IA-32 MMX technology instructions. See the
Intel
®
64 and IA-32 Architectures Software Developer’s Manual for MMX technology
coding guidelines for details.
6.2.2.7 IA-32 SSE Registers
The eight 128-bit IA-32 SSE registers (XMM0-7) are mapped on sixteen physical
Itanium floating-point register pairs FR16 - FR31. The low order 64-bits of XMM0 are
mapped to FR16{63:0}, and the high order 64-bits of XMM0 are mapped to
FR17{63:0}.
• When a value is written to an SSE register using IA-32 SSE instructions:
• The exponent field of the corresponding Itanium floating-point register (bits
80-64) is set to 0x1003E and the sign bit (bit 81) is set to 0.
• The mantissa (bits 63-0) is set to the XMM data value bits{63:0} for even
registers and bits{127:64} for odd registers.
• When a SSE register is read using IA-32 SSE instructions:
• The exponent field of the corresponding Itanium floating-point register (bits
80-64) and the sign bit (bit 81) are ignored, including any NaTVal encodings.
6.2.3 Memory Model Overview
Virtual addresses within either the Itanium or IA-32 instruction set are defined to
address the same physical memory location. Itanium instructions directly generate
64-bit virtual addresses. IA-32 instructions generate 16- or 32-bit effective addresses
that are then converted into 32-bit virtual addresses by IA-32 segmentation. 32-bit
virtual addresses are then converted into 64-bit virtual addresses by zero extending to
64-bits. Zero extension places all IA-32 memory references in the lower 4G-bytes of
the 64-bit virtual address space within virtual region 0. Virtual addresses generated by
either instruction set are then translated into physical addresses using memory
management mechanisms defined in
Chapter 4, “Addressing and Protection” in Volume
2 .
Figure 6-4. SSE Registers (XMM0-XMM7)
81 80 64 63 0
0 0x1003E XMM0-7{127:64} FR17-31, odd
81 80 64 63 0
0 0x1003E XMM0-7{63:0} FR16-30, even