Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 940 / 1898

Volume 3: Instruction Reference 3:41
cmp
Operation: if (PR[qp]) {
if ( p
1
== p
2
)
illegal_operation_fault();
tmp_nat = (register_form ? GR[ r
2
].nat : 0) || GR[ r
3
].nat;
if (register_form)
tmp_src = GR[ r
2
];
else if (imm8_form)
tmp_src = sign_ext( imm
8
, 8);
else // parallel_inequality_form
tmp_src = 0;
if ( crel == ‘eq’) tmp_rel = tmp_src == GR[ r
3
];
else if ( crel == ‘ne’) tmp_rel = tmp_src != GR[ r
3
];
else if ( crel == ‘lt’) tmp_rel = lesser_signed(tmp_src, GR[ r
3
]);
else if ( crel == ‘le’) tmp_rel = lesser_equal_signed(tmp_src, GR[ r
3
]);
else if ( crel == ‘gt’) tmp_rel = greater_signed(tmp_src, GR[ r
3
]);
else if ( crel == ‘ge’) tmp_rel = greater_equal_signed(tmp_src, GR[ r
3
]);
else if ( crel == ‘ltu’) tmp_rel = lesser(tmp_src, GR[ r
3
]);
else if ( crel == ‘leu’) tmp_rel = lesser_equal(tmp_src, GR[ r
3
]);
else if ( crel == ‘gtu’) tmp_rel = greater(tmp_src, GR[ r
3
]);
else tmp_rel = greater_equal(tmp_src, GR[ r
3
]);//‘geu’
switch ( ctype ) {
case ‘and’: // and-type compare
if (tmp_nat || !tmp_rel) {
PR[ p
1
] = 0;
PR[ p
2
] = 0;
}
break;
case ‘or’: // or-type compare
if (!tmp_nat && tmp_rel) {
PR[ p
1
] = 1;
PR[ p
2
] = 1;
}
break;
case ‘or.andcm’: // or.andcm-type compare
if (!tmp_nat && tmp_rel) {
PR[ p
1
] = 1;
PR[ p
2
] = 0;
}
break;
case ‘unc’: // unc-type compare
default: // normal compare
if (tmp_nat) {
PR[ p
1
] = 0;
PR[ p
2
] = 0;
} else {
PR[ p
1
] = tmp_rel;
PR[ p
2
] = !tmp_rel;
}
break;
}
} else {
if ( ctype == ‘unc’) {
if ( p
1
== p
2
)