4:564
Volume 4: IA-32 SSE Instruction Reference
PAVGB/PAVGW: Packed Average
(Continued)
temp[i] = zero_ext(x[i], 16) + zero_ext(y[i], 16);
res[i] = (temp[i] +1) >> 1;
}
mm1[15-0] =
res[0];
...
mm1[63-48] =
res[3];
}
Description:
The PAVG instructions add the unsigned data elements of the source operand to the
unsigned data elements of the destination register, along with a carry-in. The results of
the add are then each independently right shifted by one bit position. The high order
bits of each element are filled with the carry bits of the corresponding sum.
The destination operand is a MMX technology register. The source operand can either
be a MMX technology register or a 64-bit memory operand.
The PAVGB instruction operates on packed unsigned bytes and the PAVGW instruction
operates on packed unsigned words.
Numeric Exceptions:
None.
Protected Mode Exceptions:
#GP(0) for an illegal memory operand effective address in the CS, DS, ES, FS or GS
segments; #SS(0) for an illegal address in the SS segment; #PF(fault-code) for a page
fault; #UD if CR0.EM = 1; #NM if TS bit in CR0 is set. #MF if there is a pending FPU
exception; #AC for unaligned memory reference. To enable #AC exceptions, three
conditions must be true(CR0.AM is set; EFLAGS.AC is set; current CPL is 3).
Real Address Mode Exceptions:
Interrupt 13 if any part of the operand would lie outside of the effective address space
from 0 to 0FFFFH;
#UD if CR0.EM = 1; #NM if TS bit in CR0 is set; #MF if there is a
pending FPU exception.
Virtual 8086 Mode Exceptions:
Same exceptions as in Real Address Mode; #PF(fault-code) for a page fault; #AC for
unaligned memory references (if the current privilege level is 3).
Additional Itanium System Environment Exceptions
Itanium Reg Faults Disabled FP Register Fault if PSR.dfl is 1, NaT Register
Consumption Fault
Itanium Mem Faults VHPT Data Fault, Data TLB Fault, Alternate Data TLB Fault, Data
Page Not Present Fault, Data NaT Page Consumption Abort, Data
Key Miss Fault, Data Key Permission Fault, Data Access Rights
Fault, Data Access Bit Fault
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...