Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 1781 / 1898

Volume 4: IA-32 SSE Instruction Reference 4:479
In the extreme case, all the significant bits are shifted out to the right by leading zeros,
creating a zero result.
The processor deals with denormal values in the following ways:
• It avoids creating denormals by normalizing numbers whenever possible.
• It provides the floating-point underflow exception to permit programmers to detect
cases when denormals are created.
• It provides the floating-point denormal-operand exception to permit procedures or
programs to detect when denormals are being used as source operands for
computations.
4.7.1.7 Signed Infinities
The two infinities, +  and  , represent the maximum positive and negative real
numbers, respectively, that can be represented in the floating-point format. Infinity is
always represented by a zero significand (fraction and integer bit) and the maximum
biased exponent allowed in the specified format (for example, 255
10
for the single-real
format).
The signs of infinities are observed, and comparisons are possible. Infinities are always
interpreted in the affine sense; that is, -
 is less than any finite number and +  is
greater than any finite number. Arithmetic on infinities is always exact. Exceptions are
generated only when the use of an infinity as a source operand constitutes an invalid
operation.
Whereas denormalized numbers represent an underflow condition, the two infinity
numbers represent the result of an overflow condition. Here, the normalized result of a
computation has a biased exponent greater than the largest allowable exponent for the
selected result format.
4.7.1.8 NaNs
Since NaNs are non-numbers, they are not part of the real number line. In Figure 4-10 ,
the encoding space for NaNs in the processor floating-point formats is shown above the
ends of the real number line. This space includes any value with the maximum
allowable biased exponent and a non-zero fraction. (The sign bit is ignored for NaNs.)
The IEEE standard defines two classes of NaN: quiet NaNs (QNaNs) and signaling NaNs
(SNaNs). A QNaN is a NaN with the most significant fraction bit set; an SNaN is a NaN
with the most significant fraction bit clear. QNaNs are allowed to propagate through
most arithmetic operations without signaling an exception. SNaNs generally signal an
invalid-operation exception whenever they appear as operands in arithmetic operations.
Exceptions, as well as detailed information on how the processor handles NaNs, are
discussed in Section 4.7.2, “Operating on NaNs”.
Denormalize 0

126 0.00101011100...00
Denormal Result 0

126 0.00101011100...00
a. Expressed as an unbiased, decimal number.
Table 4-2. Denormalization Process
Operation Sign Exponent
a
Significand