Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 889 / 1898

Volume 2, Part 2: Code Examples 2:641
//
// The Translation Insertion Format looks like the following...
//
// Below is the register interface to insert entries into the TLB
//
//1) A general register contains an address,attributes,and permissions
//2) ITIR: additional info such as protection key page size info
//3) IFA: specifies the virtual page number for instruction and data
// TLB inserts
//
//Registers used:
//---------------
// | 63 53 | 52 | 51 50 | 49 12 | 11 9| 8 7 | 6 | 5 |4 1| 0 |
//GR | ig | ed | rv | ppn | ar | pl | d | a | ma | p |
//
// ITIR | rv {63:32} | key {31:8} | ps {7:2} | rv {1:0}|
//
//IFA | vpn {63:12}| ignored {11:0} |
//
//RR[vrn] | reserved{63:32} | rid {31:8}| ignored {7:2) | rv{1} | ignored {0}|
//
//
//where
//ig = ignored bits
//rv= reserved bits
//p = present bit
//ma = memory attribute
//a = accessed bit
//d = dirty bit
//pl= privilege level
//ar= access rights
//ppn= physical page number
//ed= exception deferral
//ps= page size of mapping (2**ps)
//vpn= virtual page number
//
// Setup virtual page number
//
// NOTE:The virtual page number depends on a translation’s
//page size.
//
// Add entry for TEXT section
movl r2 = 0x0
;;
mov cr.ifa = r2
//setup ITIR (Interruption TLB Insertion Register)
movl r3=( ( 24 << 2 ) | ( 0 << 8 ) ) // set page size to 16 MB
;;
mov cr.itir = r3
//now setup the general register to use with itr (insert translation
//register), use physical page of zero
movl r10 =( (1 << 52 )| ( 0x00000000 << 12 )|( 3 << 9 )|( 0 << 7 )| \
(1 <<6 ) | ( 1 << 5 ) | ( 1 << 0 ))
mov r11 = r0
;;
itr.i itr[r11] = r10 // Insert translation register
//Entry for OS Data section
add r11 = 1, r11 // skip to tr next index