Volume 3: Resource and Dependency Semantics
3:373
may expand to contain other classes, and that when fully expanded, a set of
classes (e.g., the readers of some resource) may contain the same instruction
multiple times.
• The syntax ‘
x
\
y
’ where
x
and
y
are both instruction classes, indicates an unnamed
instruction class that includes all instructions in instruction class
x
but that are not
in instruction class
y
. Similarly, the notation ‘
x
\
y
\
z
’ means all instructions in
instruction class
x
, but that are not in either instruction class
y
or instruction class
z
.
• Resources on separate rows of a table are independent resources. This means that
there are no serialization requirements for an event which references one of them
followed by an event which uses a different resource. In cases where resources are
broken into subrows, dependencies only apply between instructions within a
subrow. Instructions that do not appear in a subrow together have no
dependencies (reader/writer or writer/writer dependencies) for the resource in
question, although they may still have dependencies on some other resource.
• The dependencies listed for pairs of instructions on each resource are not unique
–
the same pair of instructions might also have a dependency on some other resource
with a different semantics of dependency. In cases where there are multiple
resource dependencies for the same pair of instructions, the most stringent
semantics are assumed:
instr
overrides
data
which overrides
impliedF
which
overrides
implied
which overrides
none
.
• Arrays of numbered resources are represented in a single row of a table using the
% notation as a substitute for the number of the resource. In such cases, the
semantics of the table are as if each numbered resource had its own row in that
table and is thus an independent resource. The range of values that the % can take
are given in the “Resource Name” column.
• An asterisk ‘*’ in the “Resource Name” column indicates that this resource may not
have a physical resource associated with it, but is added to enforce special
dependencies.
• A pound sign ‘#’ in the “Resource Name” column indicates that this resource is an
array of resources that are indexed by a value in a GR. The number of individual
elements in the array is described in the detailed description of each resource.
• The “Semantics of Dependency” column describes the outcome given various
serialization and instruction group boundary conditions. The exact definition for
each keyword is given in
.
Table 5-1.
Semantics of Dependency Codes
Semantics of
Dependency Code
Serialization Type Required
Effects of Serialization Violation
instr
Instruction Serialization (See
Atomic: Any attempt to read a resource after one or
more insufficiently serialized writes is either the
value previously in the register (before any of the
unserialized writes) or the value of one of any
unserialized writes. Which value is returned is
unpredictable and multiple insufficiently serialized
reads may see different results. No fault will be
caused by the insufficient serialization.
data
Data Serialization (See
)
implied
Instruction Group Break. Writer and reader must be in
separate instruction groups. (See
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...