2:62
Volume 2, Part 1: Addressing and Protection
The processor does not manage the VHPT or perform any writes into the table.
Software is responsible for insertion of entries into the VHPT (including replacement
algorithms), dirty/access bit updates, invalidation due to purges and coherency in a
multiprocessor system. The processor does not ensure the TLBs are coherent with the
VHPT memory image.
If software needs to control the entries inserted into the TLB more explicitly, or
programs the VHPT with differing mappings for the same virtual address range, it may
need to take additional action to ensure forward progress.
4.1.5.1
VHPT Configuration
The Page Table Address (PTA) register determines whether the processor is enabled to
walk the VHPT, anchors the VHPT in the virtual address space, and controls VHPT size
and configuration information. The VHPT can be configured as either a per-region
virtual linear page table structure (8-byte short format) or as a single large hash page
table (32-byte long format). No mixing of formats is allowed within the VHPT.
To implement a per-region linear page table structure an operating system would
typically map the leaf page table nodes with small backing virtual translations. The size
of the table is expanded to include all possible virtual mappings, effectively creating a
large per-region flat page table within the virtual address space.
To implement a single large hash page table, the entire VHPT is typically mapped with a
single large pinned virtual translation placed in the translation registers and the size of
the table is reduced such that only a subset of all virtual mappings can be resident
within the table. Operating systems can tune the size of the hash page table based on
the size of physical memory and operating system performance requirements.
4.1.5.2
VHPT Searching
When enabled, the processor’s VHPT walker searches the VHPT for a translation after a
failed instruction or data TLB search. The VHPT walker checks only the specific VHPT
entry addressed by the short- or the long-format hash function, as selected by PTA.vf.
If additional TLB misses are encountered during the VHPT access, a VHPT Translation
Figure 4-9.
Virtual Hash Page Table (VHPT)
TLB
Virtual Address
Hashing
Function
VHPT
Optional Collision Search Chain
Optional Operating System Page Tables
Region
Registers
rid
vpn
PTA
2
PTA.size
PTA.base
ps
TC
Install
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...