Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 583 / 1898

Volume 2, Part 1: Processor Abstraction Layer 2:335
11.7.4 Virtualization Optimizations
After the PAL_VP_INIT_ENV procedure is called, execution of the virtualized
instructions listed in
Table 3-10, “Virtualized Instructions” on page 2:44 with
PSR.vm==1 results in virtualization intercepts to the VMM. Virtualization optimizations
reduce overall virtualization overhead by allowing these instructions to execute, with
PSR.vm==1, without causing intercepts to the VMM. There are two types of
virtualization optimizations – global and local. Local virtualization optimizations are
further divided into virtualization accelerations and virtualization disables.
Global virtualization optimizations are specified during initialization of the virtual
environment (i.e., during PAL_VP_INIT_ENV). The specified optimizations are
applicable to all the virtual processors running in the virtual environment. See
Section
11.7.4.1, “Global Virtualization Optimizations” for details on the global virtualization
optimizations supported in the architecture.
Local virtualization optimizations are specified during the creation of the virtual
processor (i.e., during PAL_VP_CREATE). The optimization settings were specified in the
VPD and hence local to each virtual processor. The VMM can specify different local
optimization settings for different virtual processors. The two classes of local
virtualization optimizations are:
• Virtualization accelerations – Virtualization accelerations optimize the execution of
virtualized instructions by supporting fast access to the virtual instance of the
27 ptc_g Due to
ptc.g
instruction.
28 ptc_ga Due to
ptc.ga
instruction.
29 ptr_d Due to ptr.d instruction.
30 ptr_i Due to
ptr.i
instruction.
31 thash Due to
thash
instruction.
32 ttag Due to
ttag
instruction.
33 tpa Due to
tpa
instruction.
34 tak Due to
tak
instruction.
35 ptc_e Due to ptc.e instruction.
36 cover Due to
cover
instruction.
37 rfi Due to
rfi
instruction.
38 bsw_0 Due to
bsw.0
instruction.
39 bsw_1 Due to
bsw.1
instruction.
40 vmsw Due to
vmsw
instruction.
41 probe Due to probe instruction.
All
other
values Reserved Reserved for future expansion.
Figure 11-15. PAL Virtualization Intercept Handoff Opcode (GR25)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Opcode {31:6} Reserved
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
b m Reserved Opcode {40:32}
Table 11-22. PAL Virtualization Intercept Handoff Cause (GR24) (Continued)
Value Cause Description