Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 1454 / 1898

4:152 Volume 4: Base IA-32 Instruction Reference
FPREM—Partial Remainder (Continued)
The FPREM instruction gets its name “partial remainder” because of the way it
computes the remainder. This instructions arrives at a remainder through iterative
subtraction. It can, however, reduce the exponent of ST(0) by no more than 63 in one
execution of the instruction. If the instruction succeeds in producing a remainder that is
less than the modulus, the operation is complete and the C2 flag in the FPU status word
is cleared. Otherwise, C2 is set, and the result in ST(0) is called the
partial remainder .
The exponent of the partial remainder will be less than the exponent of the original
dividend by at least 32. Software can re-execute the instruction (using the partial
remainder in ST(0) as the dividend) until C2 is cleared.
Note: While executing such a remainder-computation loop, a higher-priority inter-
rupting routine that needs the FPU can force a context switch in-between the
instructions in the loop.
An important use of the FPREM instruction is to reduce the arguments of periodic
functions. When reduction is complete, the instruction stores the three least-significant
bits of the quotient in the C3, C1, and C0 flags of the FPU status word. This information
is important in argument reduction for the tangent function (using a modulus of
 /4),
because it locates the original angle in the correct one of eight sectors of the unit circle.
Operation
D

exponent(ST(0)) - exponent(ST(1));
IF D < 64
THEN
Q

Integer(TruncateTowardZero(ST(0)

ST(1)));
ST(0)

ST(0) - (ST(1)

Q);
C2

0;
C0, C3, C1

LeastSignificantBits(Q); (* Q2, Q1, Q0 *)
ELSE
C2

1;
N

an implementation-dependent number between 32 and 63;
QQ

Integer(TruncateTowardZero((ST(0)

ST(1)) / 2
(D

N)
));
ST(0)

ST(0) - (ST(1)

QQ

2
(D

N)
);
FI;
FPU Flags Affected
C0 Set to bit 2 (Q2) of the quotient.
C1 Set to 0 if stack underflow occurred; otherwise, set to least
significant bit of quotient (Q0).
C2 Set to 0 if reduction complete; set to 1 if incomplete.
C3 Set to bit 1 (Q1) of the quotient.
Additional Itanium System Environment Exceptions
Itanium Reg Faults Disabled FP Register Fault if PSR.dfl is 1, NaT Register Consumption
Abort.