2:610
Volume 2, Part 2: External Interrupt Architecture
The Interval Time Counter (ITC) gets updated at a fixed relation to the processor clock.
The ITM, Interval Timer Match, is used to determine when a interval timer interrupt is
generated. When the ITC matches the ITM and the timer is unmasked via ITV then an
interrupt will be generated.
//
// routine to reset the interval timer to zero..
//
ENTRY(em_timer_reinit)
mov ar.itc=r0
// reset itimer counter
br.ret.spnt.few rp
END(em_timer_reinit)
//
// routine to setup the interval timer.
//
// 1) setup the interval timer vector
// 2) initialize the time counter to zero
// 3) initialize the match register
//
// INPUTS: timermatch -- value to initialize ITM register with.
//
vector number -- vector to interrupt with
// OUTPUTS: none
//
ENTRY(enable_minterval)
alloc
r14=ar.pfs,0x2,0,0,0 // get ready for input parameters
mov
ar.itc=r0
// initialize counter to zero
;;
mov
cr.itm=r32
// set match register
;;
srlz.d
mov
cr.itv=r33
// set interval timer vector
;;
srlz.d
// make sure it goes through
br.ret.sptk.few rp
// return
.endp
Since the ITC gets updated at a fixed relation to the processor clock, in order to find out
the frequency at run time, one can use a firmware call to obtain the input frequency
information to the interval time. Using this frequency information the ITM can be set to
deliver an interrupt at a specific time interval (i.e. for operating system scheduling
purposes). Assuming the frequency information returned by the firmware is in ticks per
second, the programmer could use a time-out delta for delivering a timer interrupt
every 10 milliseconds as follows:
timeout_delta=ticks_per_second/100;
where
ticks_per_second
is the frequency value returned by the firmware and
timeout_delta
will be the value added to the ITC for setting the next ITM. Therefore, the
ITC is left free running, but the ITM must be updated upon every timer interrupt with its
next time out match value, i.e. ITM = ITC +
timeout_delta
.
The only issue with this setup is if the timer interrupt delivery is delayed beyond the
point of the original intended delivery time (i.e. ITC > ITM). This could happen if
interrupts were disabled or blocked by the operating system/device driver longer than
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...