232
Intel
®
Itanium
®
Architecture Software Developer’s Manual, Rev. 2.3
Generic Performance Counter Data Register Fields . . . . . . . . . . . . . . . . . . . . 2:157
Generic Performance Counter Configuration Register Fields (PMC[4]..PMC[p]) . . . . . . 2:157
Reading Performance Monitor Data Registers . . . . . . . . . . . . . . . . . . . . . . . 2:158
Performance Monitor Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:159
Performance Monitor Overflow Register Fields (PMC[0]...PMC[3]) . . . . . . . . . . . . . 2:161
Writing of Interruption Resources by Vector. . . . . . . . . . . . . . . . . . . . . . . . . 2:166
ISR Values on Interruption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:168
Itanium
®
Traps . . . . . . . . . . . . . . . . . . . . . . . . . . 2:170
Interruption Vectors Sorted Alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . 2:171
Intercept Code Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:234
Segment Prefix Override Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:234
Gate Intercept Trap Code Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:235
System Flag Intercept Instruction Trap Code Instruction Identifier . . . . . . . . . . . . . 2:236
IA-32 System Register Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:240
IA-32 System Segment Register Fields (LDT, GDT, TSS) . . . . . . . . . . . . . . . . . 2:242
IA-32 EFLAG Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:244
IA-32 Control Register Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:247
IA-32 Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:254
Instruction Cache Coherency Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:265
IA-32 Load/Store Sequentiality and Ordering . . . . . . . . . . . . . . . . . . . . . . . . 2:265
IA-32 Interruption Vector Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:275
IA-32 Interruption Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:275
FIT Entry Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:288
GR38 Reset Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:290
function Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:291
status Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:292
Geographically Significant Processor Identifier Fields . . . . . . . . . . . . . . . . . . . 2:293
state Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:294
Processor State Parameter Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:299
Software Recovery Bits in Processor State Parameter . . . . . . . . . . . . . . . . . . . 2:301
PSP Bit Settings for Unconsumed Data-poisoning Events on MCA. . . . . . . . . . . . . 2:302
11-10 NaT Bits for Saved GRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:305
11-11 function Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:305
11-12 Processor State Parameter Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:308
11-13 function Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:310
11-14 PMI Events and Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:311
11-15 PMI Message Vector Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:311
11-16 Virtual Processor Descriptor (VPD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:326
11-17 Virtual Processor Descriptor (VPD) – VPSR . . . . . . . . . . . . . . . . . . . . . . . . 2:328
11-18 Virtual Processor Descriptor (VPD) – VCR[0-127] . . . . . . . . . . . . . . . . . . . . . 2:329
11-19 Virtualization Acceleration Control (
) Fields . . . . . . . . . . . . . . . . . . . . . . . 2:329
11-20 Virtualization Disable Control (
vdc
) Fields. . . . . . . . . . . . . . . . . . . . . . . . . . 2:330
11-21 IVA Settings after PAL Virtualization-related Procedures and Services. . . . . . . . . . . 2:332
11-22 PAL Virtualization Intercept Handoff Cause (GR24) . . . . . . . . . . . . . . . . . . . . 2:334
11-23 Global Virtualization Optimizations Summary . . . . . . . . . . . . . . . . . . . . . . . . 2:336
11-24 Synchronization Requirements for Virtualization Opcode Optimization . . . . . . . . . . . 2:336
11-25 Behavior of Guest MOV-from-AR.ITC Instruction in Virtual Environment . . . . . . . . . . 2:337
11-26 Virtualization Accelerations Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:338
11-27 Detection of Virtual External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:339
11-28 Synchronization Requirements for Virtual External Interrupt Optimization . . . . . . . . . 2:339
11-29 Interruptions when Virtual External Interrupt Optimization is Enabled . . . . . . . . . . . 2:340
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...