Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 513 / 1898

Volume 2, Part 1: Itanium
®
Architecture-based Operating System Interaction Model with IA-32 Applications 2:265
• For all processors in the coherence domain, local and remote instruction cache
coherency on all processors is enforced for any store generated by any processor
running the IA-32 instruction set.
• For all processors in the coherence domain, instruction cache coherency on all
processors is enforced for all coherent I/O traffic. (For non-coherent I/O, a
processor may or may not see the results of an I/O operation.)
• For all processors in the coherence domain, instruction cache coherency is not
enforced for stores generated by any processor running the Itanium instruction set.
To ensure instruction cache coherency, Itanium architecture-based code must use
the code sequence defined in
Section 4.4.6.2, “Memory Consistency” on page 1:72 .
10.6.10 IA-32 Memory Ordering
IA-32 memory ordering follows the Pentium
III
defined processor ordered model for
cacheable and uncacheable memory. IA-32 processor ordered memory references are
mapped onto the Itanium memory ordering model as follows:
• All IA-32 stores have release semantics. Except for IA-32 stores to
write-coalescing memory that are unordered. Subsequent loads are allowed to
bypass buffered local store data before it is globally visible. The amount of store
buffering is model specific and can vary across processor generations.
• All IA-32 loads have acquire semantics. Some high performance processor
implementations may speculatively issue acquire loads into the memory system for
speculative memory types, if and only if the loads do not appear to pass other loads
as observed by the program. If there is a coherency action that would result in the
appearance to the program of a load bypassing other load, the processor will
reissue the load operation(s) in program order.
• All IA-32 read-modify-write or locked instructions have memory fence semantics.
All buffered stores are flushed.
• IA-32 IN, OUT and serializing operations (as defined in the Intel
®
64 and IA-32
Architectures Software Developer’s Manual ) have memory fence semantics.
In addition, the processor will wait for completion (acceptance by the platform) of
the IN or OUT before executing the next instruction. All buffered stores are flushed
before the IN or OUT operation.
• IA-32 SFENCE has release semantics and will flush all buffered stores.
Table 10-6. Instruction Cache Coherency Rules
Originating
Instruction Set
Local Processor External Processor Coherent, I/O Non-Coherent I/O
IA-32 Coherent Coherent
Coherent
Maybe
Non-Coherent
Intel Itanium May be
Non-coherent May be
Non-coherent
Table 10-7. IA-32 Load/Store Sequentiality and Ordering
IA-32 Memory
Reference
Uncacheable
Write
Coalescing
Cacheable
store sequential
release
a
non-sequential
unordered non-sequential
release
b
load sequential
acquire
a
non-sequential
unordered non-sequential
acquire
b