Volume 1, Part 2: Introduction to Programming for the Intel
®
Itanium
®
Architecture
1:141
or WAW register dependencies, they can be issued without hardware checks for register
dependencies between instructions. Both of the examples below show two instruction
groups separated by stops (indicated by double semicolons):
ld8 r1=[r5] ;; // First group
add r3=r1,r4
// Second group
A more complex example with multiple register flow dependencies is shown below:
ld8 r1=[r5]
// First group
sub r6=r8,r9 ;;// First group
add r3=r1,r4
// Second group
st8 [r6]=r12
// Second group
All instructions in a single instruction group may not necessarily issue in parallel
because specific implementations may not have sufficient resources to issue all
instructions in an instruction group.
2.3.3
Bundles and Templates
In assembly code, each 128-bit bundle is enclosed in curly braces and contains a
template specification and three instructions. Thus, a stop may be specified at the end
of any bundle or in the middle of a bundle by using one of two special template types
that implicitly include mid-bundle stops.
Each instruction in a bundle is 41-bits long. Five other bits are used by a template-type
specification. Bundle templates enable processors based on the Itanium architecture to
dispatch instructions with simple instruction decoding, and stops enable explicit
specification of parallelism.
There are five slot types (M, I, F, B, and L), six instruction types (M, I, A, F, B, L), and
12 basic template types (MII, MI_I, MLX, MMI, M_MI, MFI, MMF, MIB, MBB, BBB, MMB,
MFB). Each basic template type has two versions: one with a stop after the third slot
and one without. Instructions must be placed in slots corresponding to their instruction
types based on the template specification, except for A-type instructions that can go in
either I or M slots. For example, a template specification of
.MII
means that of the
three instructions in a bundle, the first is a memory (
M
) or A-type instruction, and the
next two are ALU integer (
I
) or A-type instructions:
{ .mii
ld4 r28=[r8]
// Load a 4-byte value
add r9=2,r1
// 2+r1 and put in r9
add r30=1,r1
// 1+r1 and put in r30
}
For readability, most code examples in this book do not specify templates or braces.
Note:
Bundle boundaries have no direct correlation with instruction group boundaries
as instruction groups can extend over an arbitrary number of bundles. Instruc-
tion groups begin and end where stops are set in assembly code, and dynami-
cally whenever a branch is taken or a stop is encountered.
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...