Volume 1, Part 1: Floating-point Programming Model
1:107
performance on implementations that do not implement denormal handling in
hardware. When the Flush-to-Zero mode is enabled, floating-point exception software
assist traps will not occur when producing tiny results.
5.4.4
Integer Invalid Operations
Floating-point to integer conversions which are invalid (in the IEEE sense) signal an
Invalid Operation Floating-Point Exception fault. If the IEEE Invalid Operation trap is
disabled, then the largest magnitude negative integer is the result, even for unsigned
integer operations.
5.4.5
Definition of Arithmetic Operations
Arithmetic operations are those that compute on the operands by treating each
operand’s encoding as a value, whereas non-arithmetic operations perform bit
manipulations on the input operands without regard to the value represented by the
encoding (except for NaTVal detection). Non-arithmetic instructions do not cause
Floating-point Exception faults or traps, but can cause the Disabled Floating-point
Register fault.
5.4.6
Definition and Propagation of NaNs
Signaling NaNs have a zero in the most significant fractional bit of the significand. Quiet
NaNs have a one in the most significant fractional bit of the significand. This definition
of signaling and quiet NaNs easily preserves “NaNness” when converting between
different precisions. When propagating NaNs in operations that have more than one
NaN operand, the result NaN is chosen from one of the operand NaNs in the following
priority based on register encoding fields: first
f4,
then
f2
, and lastly
f3
.
5.4.7
IEEE Standard Mandated Operations Deferred to Software
The following IEEE mandated operations will be implemented in software:
• String to floating-point conversion
• Floating-point to string conversion
• Divide (with help from
frcpa
or
fprcpa
instruction)
• Square root (with help from
frsqrta
or
fprsqrta
instruction)
• Remainder (with help from
frcpa
or
fprcpa
instruction)
• Floating-point to integer valued floating-point conversion
• Correctly wrapping the exponent for single, double, and double-extended overflow
and underflow values, as recommended by the IEEE standard
5.4.8
Additions beyond the IEEE Standard
• The fused multiply and add (
fma
,
fms
,
fnma
,
fpma
,
fpms
,
fpnma
) operations enable
efficient software divide, square root, and remainder algorithms.
• The extended range of the 17-bit exponent in the register format allows simplified
implementation of many basic numeric algorithms by the careful numeric
programmer.
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...