Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 767 / 1898

Volume 2, Part 2: MP Coherence and Synchronization 2:519
to account for both the memory ordering semantics and dependencies. It is important
to keep in mind that the observance of a dependency between two operations does not
imply an ordering relationship (from the standpoint of the memory ordering model)
between the operations as
Section 2.2.1.6 describes.
Assuming that a processor can bypass locally-written values before they are made
globally-visible implies that there is a local and a global visibility points for a memory
operation where a value always becomes locally visible before it becomes globally
visible. Since M1 and M4 can have local visibility with respect to M2 and M5 as well as
global visibility,
where m1 and M1 represent local and global visibility of memory operation 1,
respectively. There are two things to note. First, the ordering of the local visibilities of
operations M1 and M4 (m1 and m4, respectively) allow each processor to honor its data
dependencies. That is, Processor #2 honors the RAW dependency through memory
between M1 and M2 by requiring m1 to become visible before M2. Second, that these
requirements do not place any constraints on the relative ordering perceived by a
remote observer of operation M1 with M2 and M3 or of operation M4 with M5 and M6
(as the local visibilities meet the local ordering constraints that the dependencies
impose).
The code in Table 2-10 and these constraints together imply that
Thus, the outcome r1 = 1, r3 = 1, r2 = 0, and r4 = 0 is allowed because these
statements are consistent with our definition of local and global visibility. Specifically, a
value becomes locally visible before it becomes globally visible. Similar reasoning can
show that the constraints also imply that
2.2.1.9 Preventing Store Buffers from Satisfying Local Loads
In the code shown in Table 2-10 from Section 2.2.1.8 , there are no ordering constraints
between the store and acquire load from the standpoint of memory ordering semantics
(however, there is a RAW dependency through memory that forces the acquire load to
follow the store). Bypassing may not occur if doing so violates the memory ordering
constraints of memory operations between the store and the bypassing read.
Table 2-11 presents a variation on the execution in Table 2-10 from Section 2.2.1.8
that illustrates this behavior.
Table 2-11. Preventing Store Buffers from Satisfying Local Loads
Processor #0 Processor #1
st [x] = 1 // M1
mf // M2
ld.acq r1 = [x] // M3
ld r2 = [y] // M4
st [y] = 1 // M5
mf // M6
ld.acq r3 = [y] // M7
ld r4 = [x] // M8
Outcome: r1 = 1, r3 = 1, r2 = 0, and r4 = 0 is not allowed
m1 M2 M3; m1 M1
  
m4 M5 M6; m4 M4
  
r1 = 1 m1 M2
 
r3 = 1 m4 M5
 
r2 = 0 M3 M4 m1 M6 because m1 M3 and M3 M4 and M4 M6
      
r4 = 0 M6 M1
 
m1 M6 and M6 M1 m1 M1
   
m4 M4.
