Volume 2, Part 1: Itanium
®
Architecture-based Operating System Interaction Model with IA-32 Applications
2:243
10.3.1
IA-32 Current Privilege Level
PSR.cpl is the current privilege level of the processor for instruction execution
(including IA-32). PSR.cpl is used by the processor for all IA-32 descriptor
segmentation and paging permission checks. PSR.cpl is a secured register. Typical
IA-32 processors used SSD.dpl as the official privilege level of the processor. Since,
SSD.dpl is not secured from user modification, processor implementations must base
all privilege checks and state backups based on PSR.cpl.
10.3.2
IA-32 System EFLAG Register
The EFLAG (AR24) register is made of two major components, user arithmetic flags (CF,
PF, AF, ZF, SF, OF, and ID) and system control flags (TF, IF, IOPL, NT, RF, VM, AC, VIF,
VIP). None of the arithmetic or system flags affect Itanium instruction execution. The
arithmetic flags are used by the IA-32 instruction set to reflect the status of IA-32
operations, control IA-32 string operations, and control branch conditions for IA-32
instructions. System flags are typically managed by an operating system and are used
to control the overall operations of the processor. System flags are broken into two
categories, system flags that control IA-32 instruction set execution behavior and
virtualizable system flags. The NT system flag shown in bold font in
is
virtualized.
System flags AC, TF, RF, VIF, VIP, IOPL and VM directly control the execution of IA-32
instructions. These bits do not control any Itanium instructions. See
for a
complete definition these bits.
The NT bit does not directly control the execution of any IA-32 or Itanium instructions.
All IA-32 instructions that modify this bit is intercepted (e.g. IRET, Task Switches)
See
Table 10-3, “IA-32 EFLAG Field Definition”
for the behavior on IA-32 and Itanium
instruction reads/writes to this application register.
10.3.2.1
Virtualized Interrupt Flag
To provide for virtualization of IA-32 code, the IF bit is virtualizable in the context of an
operating system. Interrupts are enabled for IA-32 instructions, if
(PSR.i and
(~CFLG.if or EFLAG.if))
is true. For Itanium architecture-based code, interrupts are
enabled if PSR.i is 1.
An optional System Flag intercept trap can be generated if CFLG.ii is 1, and the IF-flag
changes state due to IA-32 code executing CLI, STI, or POPF. See
“IA-32 Control Registers” on page 2:246
for CFLG details. Using this model,
virtualization code can set CFLG.if to 0 and CFLG.ii to 0, IA-32 instruction set
modifications of EFLAG.if does not affect actual interrupt masking, therefore no
notification events need be sent to virtualizing software. When virtualization code,
detects and queues an external interrupt for delivery into a virtualized IA-32 operating
Figure 10-2. IA-32 EFLAG Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
reserved (set to 0)
id vip vif ac vm rf 0 nt
iopl of df if tf sf zf
0
af 0 pf 1 cf
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
reserved (set to 0)
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...