2:184
Volume 2, Part 1: Interruption Vector Descriptions
Name
Data Access-Bit vector (0x2800)
Cause
For data memory references (including IA-32), the access bit (TLB.a) in the TLB entry
for this page is 0, and the page is referenced.
Interruptions on this vector:
IR Data Access Bit fault
Data Access Bit fault
Parameters
IIP, IPSR, IIPA, IFS – are defined; refer to
for a detailed description.
ITIR – The ITIR contains default translation information for the address contained in the
IFA. The access key field within this register is set to the region id value from the
referenced region register. The ITIR.ps field is set to the RR.ps field from the referenced
region register. All other fields are set to 0.
IFA – Faulting data address.
IIB0, IIB1 – If implemented, for Data Access Bit faults, the IIB registers contain the
instruction bundle pointed to by IIP. The IIB registers are undefined for IR Data Access
Bit faults. Please refer to
Section 3.3.5.10, “Interruption Instruction Bundle Registers
(IIB0-1 – CR26, 27)” on page 2:42
for details on the IIB registers.
ISR – The value for the ISR bits depend on the type of access performed and are
specified below. For mandatory RSE fill or spill references, ISR.ed is always 0. For IA-32
memory references, ISR.code, ed, ei, ni, ir, rs, na and sp are 0.
Notes
These faults can only occur in these situations:
• When PSR.dt is 1 on an IA-32 or Itanium load, store, or semaphore operation
• When PSR.dt is 1 on a
probe.fault
• When PSR.dt is 1 on an
lfetch.fault
• When PSR.rt is 1 on an RSE mandatory load/store operation
For
probe.fault
or
lfetch.fault
the ISR.na bit is set.
Software uses this fault for memory management page replacement algorithms. The
PSR.da bit can be used to suppress this fault for one executed instruction or one
mandatory RSE memory reference.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
0
0
0
code{3:0}
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
0
ed
ei
so ni ir rs sp na r w 0
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...