Volume 2, Part 1: Processor Abstraction Layer
2:395
PAL_GET_HW_POLICY
The return value
num_impacted
specifies the number of logical processors impacted by
the hardware sharing policy. The return value
la
returns the logical address of one of
the logical processors impacted by the hardware sharing policy. The return value
la
is
the same value and format of that is returned by the PAL_FIXED_ADDR procedure, see
“PAL_FIXED_ADDR – Get Fixed Geographical Address of Processor (12)” on page 2:391
for details.
If the caller is interested in identifying all the logical processors impacted by the
hardware sharing policy, this procedure will need to be called a number of times equal
to the value returned in
num_impacted
return value. For each subsequent call it needs to
increment the 'proc_num' input argument.
The logical processor this procedure is made on can only return information about how
the hardware sharing policy impacts logical processors it is sharing hardware resources
with. For example a physical processor package may contain two multi-threaded cores.
On this example implementation the hardware sharing policy only impacts the two
threads on the core and this procedure would only return the two
la
's of the threads on
that core, but would not return the
la
's of the threads on the other core. When this
procedure was made on the other core, then that procedure call would return the
la
's of
the two threads on that core.
This procedure is only supported on processors that have multiple logical processors
sharing hardware resources that can be configured. On all other processor
implementations, this procedure will return the Unimplemented procedure return
status.
Table 11-80. Hardware policies returned in
cur_policy
Value
Name
Description
0
Performance
The processor has its hardware resources configured to achieve
maximum performance across all logical processors that share
hardware with the logical processor the procedure was made on.
1
Fairness
The processor has its hardware resources configured to
approximately achieve equal sharing of competing hardware
resources among all the logical processors that share hardware
with the logical processor the procedure was made on.
2
High-priority
The processor has its hardware resources configured such that the
logical processor this procedure was called on has a greater share
of the competing hardware resources.
3
Exclusive High-priority The processor has its hardware resources configured such that the
logical processor this procedure was called on has a greater share
of the competing hardware resources. See
“PAL_SET_HW_POLICY – Set Current Hardware Resource
Sharing Policy (49)” on page 2:456
for differences between
high-priority and exclusive high priority.
4
Low-priority
The processor has its hardware resources configured such that the
logical processor this procedure was called on has a smaller share
of the competing hardware resources. This occurs when a
competing logical processor has itself set as high priority or
exclusive high priority.
All Other Values
Reserved
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
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Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
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Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
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Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
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Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...