Volume 3: Instruction Reference
3:63
fchkf
fchkf — Floating-point Check Flags
Format:
(
qp
) fchkf.
sf target
25
Description:
The flags in FPSR.
sf
.flags are compared with FPSR.s0.flags and FPSR.traps. If any flags
set in FPSR.
sf
.flags correspond to FPSR.traps which are enabled, or if any flags set in
FPSR.
sf
.flags are not set in FPSR.s0.flags, then a branch to
target
25
is taken.
The
target
25
operand, specifies a label to branch to. This is encoded in the instruction
as a signed immediate displacement (
imm
21
) between the target bundle and the bundle
containing this instruction (
imm
21
=
target
25
- IP >> 4).
The branching behavior of this instruction can be optionally unimplemented. If the
instruction would have branched, and the branching behavior is not implemented, then
a Speculative Operation fault is taken and the value specified by
imm
21
is zero-extended
and placed in the Interruption Immediate control register (IIM). The fault handler
emulates the branch by sign-extending the IIM value, adding it to IIP and returning.
The mnemonic values for
sf
are given in
.
Operation:
if (PR[
qp
]) {
switch (sf) {
case ‘s0’:
tmp_flags = AR[FPSR].sf0.flags;
break;
case ‘s1’:
tmp_flags = AR[FPSR].sf1.flags;
break;
case ‘s2’:
tmp_flags = AR[FPSR].sf2.flags;
break;
case ‘s3’:
tmp_flags = AR[FPSR].sf3.flags;
break;
}
if ((tmp_flags & ~AR[FPSR].traps) || (tmp_flags & ~AR[FPSR].sf0.flags)) {
if (check_branch_implemented(FCHKF)) {
taken_branch = 1;
IP = IP + sign_ext((
imm
21
<< 4), 25);
if (!impl_uia_fault_supported() &&
((PSR.it && unimplemented_virtual_address(IP, PSR.vm))
|| (!PSR.it && unimplemented_physical_address(IP)))
unimplemented_instruction_address_trap(0, IP);
if (PSR.tb)
taken_branch_trap();
} else
speculation_fault(FCHKF, zero_ext(
imm
21
, 21));
}
}
FP Exceptions:
None
Interruptions:
Speculative Operation fault
Taken Branch trap
Unimplemented Instruction Address trap
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...