Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 319 / 1898

Volume 2, Part 1: Addressing and Protection 2:71
4.1.9 32-bit Virtual Addressing
32-bit virtual data addressing is supported in the Itanium instruction set architecture by
three models: zero-extension, sign-extension, and pointer “swizzling.” IA-32 memory
references use the zero-extension model, all IA-32 32-bit virtual linear addresses are
zero extended into the 64-bit virtual address space.
The zero-extension model performs address computations with the
add
and
shladd
instructions while software ensures that the upper 32-bits are always zeros. This model
constrains 32-bit virtual addressing to virtual region zero. In this model, regions 1 to 7
are accessible only by 64-bit addressing.
Instruction/Data TLB Miss Raised when the VHPT walker is enabled, but the processor:
• Cannot locate the required VHPT entry, or
• The processor aborts the VHPT search for
implementation-specific reasons, or
• The VHPT walker is not implemented, or
• The referenced region specifies a non-supported
VHPT preferred page size, or
• Reserved fields or unimplemented PPN bits are
used in the translation, or
• The hash address falls into unimplemented
virtual address space, or
• The hash address matches a data debug
register.
Instruction/Data TLB Miss handlers are essentially software walkers
of the VHPT.
Data Nested TLB Raised when a Data TLB Miss, Alternate Data TLB Miss, or VHPT
Data Translation fault occurs and PSR.ic is 0 and not in-flight (e.g.,
fault within a TLB miss handler). Data Nested TLB faults enable
software to avoid overheads for potential data TLB Miss faults.
Instruction/Data Page Not Present The referenced translation’s P-bit is 0.
Instruction/Data NaT Page
Consumption A non-speculative load, store, mandatory RSE load/store, execution
on, or semaphore operation accesses a page marked with the
physical memory attribute NaTPage. See
“Not a Thing Attribute
(NaTPage)” on page 2:86 for details.
Instruction/Data Key Miss The referenced translation’s permission key is not present in the set
of valid protection key registers.
Instruction/Data Key Permission The referenced translation is denied read, write, execute permissions
by the matching protection key registers.
Instruction/Data Access Rights Page granular read, write, execute and privilege level accesses are
denied.
Data Dirty Bit The referenced translation’s Dirty bit is 0 on a store or semaphore
operation.
Instruction/Data Access Bit The referenced translation’s Access bit is 0.
Table 4-10. TLB and VHPT Search Faults (Continued)
Fault Description