4:288
Volume 4: Base IA-32 Instruction Reference
MOV—Move to/from Control Registers
Description
Moves the contents of a control register (CR0, CR2, CR3, or CR4) to a general-purpose
register or vice versa. The operand size for these instructions is always 32 bits,
regardless of the operand-size attribute. (See the
Intel Architecture Software
Developer’s Manual, Volume 3
for a detailed description of the flags and fields in the
control registers.)
When loading a control register, a program should not attempt to change any of the
reserved bits; that is, always set reserved bits to the value previously read.
At the opcode level, the
reg
field within the ModR/M byte specifies which of the control
registers is loaded or read. The 2 bits in the
mod
field are always 11B. The
r/m
field
specifies the general-purpose register loaded or read.
These instructions have the following side effects:
• When writing to control register CR3, all non-global TLB entries are flushed (see the
Intel Architecture Software Developer’s Manual, Volume 3
.
• When modifying any of the paging flags in the control registers (PE and PG in
register CR0 and PGE, PSE, and PAE in register CR4), all TLB entries are flushed,
including global entries. This operation is implementation specific for the Pentium
Pro processor. Software should not depend on this functionality in future Intel
architecture processors.
• If the PG flag is set to 1 and control register CR4 is written to set the PAE flag to 1
(to enable the physical address extension mode), the pointers (PDPTRs) in the
page-directory pointers table will be loaded into the processor (into internal,
non-architectural registers).
• If the PAE flag is set to 1 and the PG flag set to 1, writing to control register CR3
will cause the PDPTRs to be reloaded into the processor.
• If the PAE flag is set to 1 and control register CR0 is written to set the PG flag, the
PDPTRs are reloaded into the processor.
Operation
IF Itanium System Environment AND Move To CR Form THEN IA-32_Intercept(INST,MOVCR);
DEST
SRC;
Opcode
Instruction
Description
0F 22 /
r
MOV CR0,
r32
Move
r32
to CR0
0F 22 /
r
MOV CR2,
r32
Move
r32
to CR2
0F 22 /
r
MOV CR3,
r32
Move
r32
to CR3
0F 22 /
r
MOV CR4,
r32
Move
r32
to CR4
0F 20 /
r
MOV
r32,
CR0
Move CR0 to
r32
0F 20 /
r
MOV
r32,
CR2
Move CR2 to
r32
0F 20 /
r
MOV
r32,
CR3
Move CR3 to
r32
0F 20 /
r
MOV
r32,
CR4
Move CR4 to
r32
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...