Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 371 / 1898

Volume 2, Part 1: Interruptions 2:123
5.8.3.2 External Interrupt Vector Register (IVR – CR65)
A read of IVR returns the highest priority, pending, unmasked external interrupt vector,
independent of the value of PSR.i. The external interrupt vector is an 8-bit encoded
number. If there are no pending external interrupts or all external interrupts are
currently masked, IVR returns the “spurious” interrupt indication (vector 15). IVR fields
are shown in
Figure 5-7 . See “Interrupt Unmasked Condition” column in Table 5-8 on
page 2:119 for masking conditions.
IVR reads also have two atomic side effects:
• The interrupt pending bit in IRR is cleared for the reported external interrupt vector.
Subsequent IVR reads will not report the interrupt as pending unless a new
interrupt was pended for the specified interrupt vector.
• The processor marks the interrupt vector as being in-service and masks all pending
external interrupts with equal or lower priority until software writes the
end-of-interrupt (EOI) register for the in-service interrupt.
To ensure IVR side effects are observed by a given point in program execution (e.g.,
before the next IVR read, EOI write, or PSR.i write to enable external interrupt
delivery), software must perform a data serialization operation after an IVR read and
prior to that point. To ensure that the reported external interrupt vector is correctly
masked before the next IVR read, software must perform a data serialization operation
after a TPR or EOI write and prior to that IVR read.
Software must be prepared to service any possible external interrupt if it reads IVR,
since IVR reads are destructive and removes the highest priority pending external
interrupt (if any).
IVR is a read-only register; writes to IVR result in a Illegal Operation fault.
IVR reads do not issue an external INTA cycle. If the interrupt vector must be acquired
from an Intel 8259A-compatible external interrupt controller, software should perform a
load from the INTA byte. See
“Interrupt Acknowledge (INTA) Cycle” on page 2:130 for
details.
5.8.3.3 Task Priority Register (TPR – CR66)
The processor’s Task Priority Register (TPR) provides the ability to create additional
masking of external interrupts based on a “priority class.” The 240 external interrupt
vectors (16 - 255) are divided into 15 priority classes of 16 numerically contiguous
interrupt vectors each. The value written in TPR.mic masks all external interrupts of
equal or lower priority classes.
To ensure that new priority levels are established by a given point in program
execution, software must perform a data serialization operation after a TPR write and
prior to that point. For example, if PSR.i is subsequently set to 1, thus enabling
interrupts, and the new priority levels need to be in place before this enabling, a data
serialization must be performed prior to the setting of PSR.i. Similarly, if PSR.pp or
Figure 5-7. External Interrupt Vector Register (IVR – CR65)
63 8 7 0
reserved vector
56 8