Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 378 / 1898

2:130 Volume 2, Part 1: Interruptions
5.8.4.2 Interrupt and IPI Ordering
Interrupt messages from external device(s), or external interrupts routed to the
processor’s LINT pins, when present, may arrive at one or more processors and become
pending in any order. No ordering is enforced by the processor or the platform.
As observed by a receiving processor, IPIs emitted from the same issuing processor
may be pended in any order, even when the receiving processor and the issuing
processor are the same.
As observed by a receiving processor, IPIs are pended after all prior loads and stores
emitted by the same issuing processor are visible if and only if the IPI is issued with a
st.rel
(or proceeded by an
mf
), even when the receiving processor and the issuing
processor are the same. For all other cases, no ordering is implied between IPI
transactions and prior cacheable or uncached memory references.
As observed by a receiving processor, no ordering is implied between IPIs and
subsequent loads/stores from the same issuing processor, even when the receiving
processor and the issuing processor are the same. Subsequent loads or stores may
become visible before an IPI is seen as pending. Data or instruction serialization
operations, memory fences (
mf
or
mf.a
), or
st.rel
do not ensure an IPI is pending at
the target processor (including self) by a given point in program execution on the local
processor.
5.8.4.3 Interrupt Acknowledge (INTA) Cycle
Intel 8259A-compatible external interrupt controllers can not issue interrupt messages
and therefore do not specify an external interrupt vector number when the interrupt
request is generated. When accepting an external interrupt, software must inspect the
vector number supplied by the IVR register. If the vector matches the vector number
assigned to the external controller (can be ExtINT, or any other vector number based
on software convention), software must acquire the actual external interrupt vector
number from the external interrupt controller by issuing a 1-byte load from the INTA
Byte.
The INTA Byte is located within the upper half of the Processor Interrupt Block, at offset
0x1E0000 from the base. A single byte load from the INTA address causes the
processor to emit the INTA cycle on the processor system bus. An Intel
8259A-compatible external interrupt controller must respond with the actual interrupt
vector number as the data to be loaded. If two INTA cycles are required by the external
interrupt controller, the platform must provide this functionality. Any memory operation
to the INTA address other than a single byte load is undefined.
Software must issue an EOI to the local processor, to clear the interrupt in-service
indication for the vector associated with the external interrupt controller.
5.8.4.4 External Task Priority (XTP) Cycle
Some model-specific system configurations support an External Task Priority Register
(XTPR) per processor in external bus logic. A processor’s XTPR can be modified by
storing one byte of data to the processor’s XTP Byte address. This generates a special
bus transaction required to change the processor’s XTPR within the system. Please refer
to system-specific documentation for XTPR bit format and field definitions. The